參數(shù)資料
型號: XRK69774IR
廠商: EXAR CORP
元件分類: 時鐘及定時
英文描述: 1:14 LVCMOS PLL CLOCK GENERATOR
中文描述: 69774 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52
文件頁數(shù): 7/11頁
文件大小: 84K
代理商: XRK69774IR
PRELIMINARY
XRK69774
7
REV. P1.0.1
1:14 LVCMOS PLL CLOCK GENERATOR
2.0
CONFIGURATION TABLES
T
ABLE
6: F
UNCTION
C
ONTROLS
C
ONTROL
P
IN
D
EFAULT
L
OGIC
0
L
OGIC
1
MR/OE
1
Resets the output divide circuitry and serial
interface, tri-states all outputs
Enables all outputs - normal operation
PLL_EN
1
PLL bypass mode enabled. This is a test
mode in which the reference clock is provided
to the output dividers in place of the VCO
output.
PLL enabled - normal operation
STOP_CLK
1
QA[4:0], QB[4:0] and QC[3:0] outputs disabled
in Low state.
Outputs enabled, normal operation
CLK_SEL
0
CLK0 selected as PLL reference
CLK1 selected
VCO_SEL
0
VCO ÷ 2
VCO ÷ 4
T
ABLE
7: B
ANK
O
UTPUT
D
IVIDER
C
ONTROLS
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
VC0_SEL
FSEL_A
QA[4:0]
VCO_SEL
FSEL_B
QB[4:0]
VC0_SEL
FSEL_C
QC[3:0]
0
0
÷4
0
0
÷4
0
0
÷8
0
1
÷8
0
1
÷8
0
1
÷12
1
0
÷8
1
0
÷8
1
0
÷16
1
1
÷16
1
1
÷16
1
1
÷24
T
ABLE
8: F
EEDBACK
D
IVIDER
C
ONTROL
VCO_SEL
FSEL_FB1
FSEL_FB0
QFB
0
0
0
÷8
0
0
1
÷16
0
1
0
÷12
0
1
1
÷24
1
0
0
÷16
1
0
1
÷32
1
1
0
÷24
1
1
1
÷48
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