參數(shù)資料
型號: XRK697H73IR
廠商: EXAR CORP
元件分類: XO, clock
英文描述: 1:12 LVCMOS PLL CLOCK GENERATOR
中文描述: 240 MHz, OTHER CLOCK GENERATOR, PQFP52
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52
文件頁數(shù): 2/12頁
文件大?。?/td> 97K
代理商: XRK697H73IR
XRK697H73
PRELIMINARY
2
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRK697H73
F
IGURE
2. P
IN
O
UT
OF
THE
XRK697H73
XTAL
Ref
VCO
PLL
200-480MHz
FB
POWER-ON RESET
SERIAL
INTERFACE
0
1
PECL
PECL
CLK0
CLK1
CLK_SEL
REF_SEL
FB_IN
VCO_SEL
PLL_EN
FSEL_A[1:0]
FSEL_B[1:0]
FSEL_C[1:0]
FSEL_FB[2:0]
INV_CLK
STOP_DATA
STOP_CLK
MR/OE
0
1
QC0
QC1
QC2
QC3
QFB
QSYNC
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
÷2
0
1
0
1
0
1
12
3
2
2
2
DIVIDER SELECT
STOP
STOP
STOP
STOP
STOP
STOP
STOP
STOP
STOP
STOP
STOP
STOP
÷4, ÷6,
÷8, ÷12
BANK A
÷4, ÷6,
÷8, ÷10
BANK B
÷4, ÷6, ÷8,
÷10, ÷12,
÷16, ÷20
FB
÷2, ÷4,
÷6, ÷8
BANK C
Sync Pulse
VDD
VDD
VDD
VDD
40
41
42
43
44
45
46
47
48
49
50
51
52
1
26
25
24
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
10
11
12
27
28
29
30
31
32
33
34
35
36
37
38
39
13
F
Q
G
Q
V
Q
F
F
Q
V
Q
G
I
GND
QB0
VDD
QB1
GND
QB2
VDD
QB3
FB_IN
GND
QFB
VDD
FSEL_FB0
GND
___
MR/OE
VDD_PLL
STOP_CLK
STOP_DATA
FSEL_FB2
PLL_EN
REF_SEL
CLK_SEL
CLK0
CLK1
PECL
PECL
F
F
F
F
Q
V
Q
G
Q
V
Q
G
V
XRK697H73
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