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參數(shù)資料
| 型號(hào)： | XRK697H73IR |
| 廠商： | EXAR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 1:12 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 240 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 97K |
| 代理商： | XRK697H73IR |
XRK697H73
PRELIMINARY
6
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
N
OTES
:
a.
PLL locked, except when configured in bypass mode.
b.
t
()
[s] = t
()
[
°
] ÷ (fref x 360
°)
c.
Not including Qsync output
d.
T is the output period.
T
ABLE
5: AC C
HARACTERISTICS
(
CON
’
T
) (V
DD
= 3.3V +/- 5%)
S
YMBOL
C
HARACTERISTICS
CONDITION
MIN
TYP
MAX
UNIT
t
PLZ,
t
PHZ
Output Disable Time
8
ns
t
PZL,
t
PZH
Output Enable Time
8
ns
t
JIT(CC)
Cycle-to-Cycle Jitter
All outputs in same divider
config.
150
200
ps
t
JIT(PER)
Period Jitter
All outputs in same divider
config.
150
ps
t
JIT()
I/O Phase Jitter RMS (1
σ)
VCO = 400MHz
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
86
13
88
16
19
21
22
27
30
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20-3.5
0.70-2.50
0.50-1.80
0.45-1.20
0.30-1.00
0.25-0.70
0.20-0.55
0.17-0.40
0.12-0.30
0.11-0.28
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
t
LOCK
PLL Lock Time
10
ms
F
IGURE
3. T
EST
L
OAD
V
TT
Z = 50
Transmission Line
50
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