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參數(shù)資料
| 型號(hào)： | XRK799J93 |
| 廠商： | Exar Corporation |
| 英文描述： | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| 中文描述： | 智能動(dòng)態(tài)時(shí)鐘開關(guān)PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 76K |
| 代理商： | XRK799J93 |
XRK799J93
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
xr
REV. 1.0.1
6
c.
Static phase offset between the selected reference clock and the feedback signal.
d.
Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change
per cycle is averaged over the clock switch excursion. (See Applications Information section for more detail)
e.
Specification holds for a clock switch between two signals no greater than
±π
out of phase. Delta period change per
cycle is averaged over the clock switch excursion.
f.
PECL output termination is 50 ohms to VCC – 2.0V.
g.
V
PP
is the minimum differential input voltage swing required to maintain AC characteristic including SPO, device and
part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB.
h.
V
CMR
is the crosspoint of the differential input signal. Normal operation is obtained when the crosspoint is within the
V
CMR
range and the input swing lies within the V
PP
specification. Violation of V
CMR
or V
PP
impacts the SPO, device
and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB.
AC C
HARACTERISTICS
(V
CC
= 3.3 + 5%, T
A
= -40
°
C
TO
+85
°
C)
f
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NIT
C
ONDITION
f
ref
Input Reference Frequency
÷
4 feedback
40
95
MHz
Locked
f
VCO
PLL VCO Lock Range
160
380
MHz
Qa output used
for feedback
f
MAX
Output Frequency Qa[1:0]
Qb[2:0]
40
80
95
190
MHz
f
refDC
Reference Input Duty Cycle
25
75
%
t
pd
Propagation Delay
CLKn to Ext_FB (SPO)
c
CLKn to Q (Bypass)
-150
150
5
ps
ns
PLL_En=1
PLL_En=0
V
PP
Differential peak-to-peak input voltage
g
0.25
1.3
V
V
CMR
Differential input crosspoint voltage
h
V
CC
-1.7
V
CC
-0.3
V
t
skew
Output-to-Output Skew
Within Qa[1:0] or Qb[2:0]
All outputs
50
80
ps
Δ
per/cycle
Rate of change of periods
Qa[1:0]
d
Qb[2:0]
d
Qa[1:0]
e
Qb[2:0]
e
50
25
400
200
ps/
cycle
DC
Output duty cycle
45
55
%
t
jitter
Cycle-to-cyle jitter, Standard deviation (RMS)
40
ps
@ f
ref
=75MHZ
t
lock
Maximum PLL lock time
10
ms
t
r
/t
f
Output Rise/Fall time
50
700
ps
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