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參數(shù)資料
| 型號(hào)： | XRK799J93 |
| 廠商： | Exar Corporation |
| 英文描述： | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| 中文描述： | 智能動(dòng)態(tài)時(shí)鐘開(kāi)關(guān)PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | XRK799J93 |
XRK799J93
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
xr
REV. 1.0.1
8
be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be
considered when analyzing the overall skew budget of a system.
H
OT
INSERTION
AND
WITHDRAWAL
In PECL applications, a powered up driver will experience a low impedance path through an XRK799J93 input
to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input
pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input
signals.
A
CQUIRING
F
REQUENCY
L
OCK
1. While the XRK799J93 is receiving a valid CLK signal, assert Man_Override HIGH.
2. The PLL will phase and frequency lock within the specified lock time.
3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags.
4. De–assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode.
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