參數(shù)資料
型號： XRT16L2552
廠商： Exar Corporation
英文描述： 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
中文描述： 2.25V至5.5V的杜阿爾特16字節(jié)FIFO
文件頁數(shù)： 47/47頁
文件大?。?/td> 413K
代理商： XRT16L2552
xr
REV. 1.1.1
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
II
4.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 23
4.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 24
4.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 25
4.5.1 INTERRUPT GENERATION:...................................................................................................................................... 25
4.5.2 INTERRUPT CLEARING: ........................................................................................................................................... 25
T
ABLE
9: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
....................................................................................................................... 26
4.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 26
T
ABLE
10: R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
................................................................................................................... 27
4.7 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 27
T
ABLE
11: P
ARITY
SELECTION
........................................................................................................................................................ 28
4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 28
4.9 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 29
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................. 30
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 31
4.12 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 31
4.13 ALTERNATE FUNCTION REGISTER (AFR) - READ/WRITE ..................................................................... 31
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 32
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 32
4.16 ENHANCED FEATURE REGISTER (EFR) .................................................................................................. 32
T
ABLE
12: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
........................................................................................................................ 33
4.17 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 34
T
ABLE
13: UART RESET CONDITIONS FOR CHANNELS A AND B ......................................................................................... 35
T
YPICAL
PACKAGE
THERMAL
RESISTANCE
DATA
(M
ARGIN
OF
ERROR
: ± 15%) ................................................35
A
BSOLUTE
M
AXIMUM
R
ATINGS
.....................................................................................................................36
ELECTRICAL CHARACTERISTICS................................................................................36
DC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................36
AC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................37
F
IGURE
14. C
LOCK
T
IMING
............................................................................................................................................................. 38
F
IGURE
15. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
F
OR
C
HANNELS
A & B................................................................................................. 38
F
IGURE
17. D
ATA
B
US
W
RITE
T
IMING
............................................................................................................................................ 39
F
IGURE
16. D
ATA
B
US
R
EAD
T
IMING
.............................................................................................................................................. 39
F
IGURE
18. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B ......................................................... 40
F
IGURE
19. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B ....................................................... 40
F
IGURE
20. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
]
FOR
C
HANNELS
A & B........................................ 41
F
IGURE
21. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
]
FOR
C
HANNELS
A & B......................................... 41
F
IGURE
22. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A & B ........................... 42
F
IGURE
23. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
]
FOR
C
HANNELS
A & B ............................ 42
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)..............................................43
PACKAGE DIMENSIONS (44 PIN PLCC).......................................................................44
R
EVISION
H
ISTORY
......................................................................................................................................45
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
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