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參數(shù)資料
| 型號： | XRT5997IVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 21/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1 7CH 3.3V 100TQFP |
| 標準包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 7/7 |
| 規(guī)程： | E1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | XRT5997IVTR-F-ND |
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XRT5997
28
Rev. 1.0.0
2.3
The “Peak Detector and Slicer Block
After the incoming line signal has passed through the
Receive Equalizer block, it will next be routed to the
“Slicer” block. The purpose of the “Slicer” block is to
quantify a given bit-period (or symbol) within the incom-
ing line signal as either a “1” or a “0”.
2.3
The “LOS Detector” block
The LOS Detector block, within each channel (of the
XRT5997 device) was specifically designed to comply
with the “LOS Declaration/Clearance” requirements per
ITU-T G.775. As a consequence, the channel will
declare an LOS Condition, (by driving the “RxLOS”
output pin “high”) if the received line signal amplitude
drops to –20dB or below. Further, the channel will clear
the LOS Condition if the signal amplitude rises back up
to –15dB or above. Figure 10 presents an illustration
that depicts the signal levels at which a given channel
(within the XRT5997 device) will assert and clear LOS.
0 dB
-6 dB
-9dB
-35dB
Maximum Cable Loss for E1
LOS Signal Must be Declared
LOS Signal Must be Cleared
LOS Signal may be Cleared or Declared
Figure 10. Illustration of the Signal Levels that the Receiver Sections
(within XRT5997 device) will declare and clear LOS
Timing Requirements associated with Declaring and
Clearing the LOS Indicator. The XRT5997 device was
designed to meet the ITU-T G.775 specification timing
requirements for declaring and clearing the LOS indica-
tor. In particular, the XRT5997 device will declare an
LOS, between 10 and 255 UI (or E1 bit-periods) after
the actual time the LOS condition occurred. Further,
the XRT5997 device will clear the LOS indicator within
10 to 255 UI after restoration of the incoming line
signal. Figure 11 illustrates the LOS Declaration and
Clearance behavior, in response to first, the “Loss of
Signal” event and then afterwards, the restoration of
the signal.
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參數(shù)描述 |
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| XRT59L81IG-F | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 BITS Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| XRT59L81IGTR-F | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 BITS Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| XRT59L91 | 制造商:EXAR 制造商全稱:EXAR 功能描述:Single-Chip E1 Line Interface Unit |
| XRT59L91ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CH E1 AFE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT59L91ID | 制造商:Exar Corporation 功能描述: |
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