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參數(shù)資料
| 型號(hào)： | XRT71D03 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 14/22頁 |
| 文件大小： | 254K |
| 代理商： | XRT71D03 |
XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
á
12
The XRT71D03 DS3/E3 Jitter Attenuator IC consists
of the following functional blocks:
The Jitter-Attenuator PLL
Timing Control Block
The 2-Channel 16/32 Bit FIFO
Serial Microprocessor Interface
1.0
1.1
1.1.1
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as short term
variations of the significant instants of a digital signal
from their ideal positions in time. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
JITTER ATTENUATOR PLL
B
ACKGROUND
I
NFORMATION
:
Definition of Jitter
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
1.1.2
SONET STS-1 to DS3 Mapping
SONET equipment jitter criteria are specified as:
i) Jitter Transfer
ii) Jitter Tolerance
iii) Jitter Generation
1.2
J
ITTER
T
RANSFER
C
HARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 7
F
IGURE
6. I
LLUSTRATION
OF
OF
A
TYPICAL
C
HANNEL
_
N
OF
THE
XRT71D03 (
CONFIGURED
TO
OPERATE
IN
THE
H
OST
M
ODE
)
HOST
Reset
16/32 Bit FIFO
Microprocessor Serial
Interface
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRCLK_n
RRPOS_n
RRNEG_n
RRCLKES
FL_n
RCLK_n
RPOS_n
RNEG_n
ICT
CS SDI SDO SClk
MClk_n
Smoothed
Clock
Jittery
Clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT71D03IV | Telecommunication IC |
| XRT71D00 | E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER |
| XRT71D00IQ | E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER |
| XRT71D04IV | 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER |
| XRT7298IP | PCM Transmitter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT71D03ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CH T3/E3JA w/T73LC03A RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT71D03IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03IV-F | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT71D03IVTR-F | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT71D04 | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER |
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