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參數(shù)資料
| 型號： | XRT71D03 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 254K |
| 代理商： | XRT71D03 |
XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.0
á
2
PIN DESCRIPTIONS
PIN DESCRIPTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
1
AVDD
****
Analog Power Supply = 5V±5% or 3.3V±5%
2
GND
****
Digital Power Supply = 5V±5% or 3.3V±5%
3
RRCLK_0
O
Received Recovered Output (De-jittered) Clock - channel 0:
Output the de-jittered or smoothed clock if the jitter attenuator is enabled. The
de-jittered data, RRPOS/RRNEG are clocked to this signal.
If RRCLKES is “l(fā)ow”, RRPOS/RRNEG will be updated at the falling edge of
RRCLK.
If RRCLKES is “high”, RRPOS/RRNEG will be updated at the rising edge of
RRCLK.
4
RRPOS_0
O
Received Recovered Positive Data (De-Jittered) Output - channel
0:
De-jittered positive data output. Updated on the rising or falling edge of
RRCLK, depending upon the state of the RRCLKES input pin (or bit-field set-
ting).
5
RRNEG_0
O
Received Recovered Negative Data (De-Jittered) Output - channel
0:
De-jittered negative data output. Updated on the rising or falling edge of
RRCLK, depending upon the state of the RRCLKES input pin (or bit-field set-
ting).
6
RRCLKES
I
Received Recovered Clock Edge Select Input:
Hardware Mode:
1. When RRCLKES = “0”, then RRPOS and RRNEG are updated on the fall-
ing edge of RRCLK
2. When RRCLKES = “1”, then RRPOS and RRNEG are updated on the rising
edge of RRCLK
N
OTE
:
This applies to all channels.
Host Mode
Connect this pin to GND when the 71D03 is configured in the Host Mode.
Internal 50 K Ohm pull-down resistor.
7
NC
No Connection
8
Rest
I
Reset Input.
(Active-Low):
A high-low transition will re-center the internal FIFO, and will clear the Com-
mand Registers (for Host Mode operation). Resetting this pin may corrupt data
within the device.
For normal operation, pull this pin to VDD.
Internal 50 K Ohm pull-up resistor.
9
DS3/E3_1
I
DS3/E3 Select Input - channel 1
:
This pin along with the STS-1 mode select pin selects the operating mode. The
following table provides the configuration:
STS-1
DS3/E3
XRT71D04 Operating Mode
0 0 DS3 (44.736 MHz)
0 1 E3 (34.368 MHz)
1 0 STS-1 (51.84 MHz)
1 1 E3 (34.368 MHz)
Internal 50 K Ohm pull-down resistor.
10
VDD
****
Digital Power Supply = 5V±5% or 3.3V±5%
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT71D03IV | Telecommunication IC |
| XRT71D00 | E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER |
| XRT71D00IQ | E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER |
| XRT71D04IV | 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER |
| XRT7298IP | PCM Transmitter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT71D03ES | 功能描述:時鐘合成器/抖動清除器 3CH T3/E3JA w/T73LC03A RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT71D03IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03IV-F | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT71D03IVTR-F | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT71D04 | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER |
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