參數(shù)資料
型號: XRT71D04
廠商: Exar Corporation
英文描述: 4-Channel E3/DS3/STS-1 Jitter Attenuator,STS-1 to DS3 Desynchronizer(達到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器)
中文描述: 4通道E3/DS3/STS-1抖動衰減器,STS - 1的到DS3 Desynchronizer(達到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器)
文件頁數(shù): 11/21頁
文件大?。?/td> 223K
代理商: XRT71D04
á
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
PRELIMINARY
REV. P1.0.2
10
SYSTEM DESCRIPTION
The XRT71D04 is an integrated 4-channel E3/DS3/
STS-1 jitter attenuator that attenuates the jitter from
the input clock and data. The jitter attenuation perfor-
mance meets the latest specifications such as Bellcore
GR-499 CORE,GR-253 CORE, ETSI TBR24,ITU-T
G.751,ITU-T G.752 and ITU-T G.755 standards.
In addition, the XRT71D04 also meets both the map-
ping and pointer adjustment jitter generation criteria
for both Category I and Category II interfaces as
specified in Bellcore GR-253.
The XRT71D04 also meets the DS3 wander specifi-
cation that apply to SONET and asynchronous inter-
faces as specified in the ANSI T1.105.03b 1997 stan-
dard.
Additionally, to support loop-timing applications, the
XRT71D04 can also be used to reduce and limit the
amount of jitter in the recovered line clock signal.
Figure 3 presents a simple block diagram of the
XRT71D04, when it is configured to operate in the
Hardware Mode and Figure 4 presents a simple block
diagram of the XRT71D04, when it is configured to
operate in the Host Mode.
F
IGURE
3. I
LLUSTRATION
OF
A
TYPICAL
C
HANNEL
-
N
OF
THE
XRT71D04
CONFIGURED
TO
OPERATE
IN
THE
H
ARD
-
WARE
M
ODE
FSS
HOST
RST
DS3/E3_chn
16/32 Bit FIFO
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRCLKn
RRPOSn
RRNEGn
FLn
DJAn
RClkn
RCLKES
RPOSn
RNEGn
ICT
MCLKn
Jittery
Clock
Smoothed
Clock
RRCLKES
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