參數(shù)資料
型號(hào): XRT71D04
廠商: Exar Corporation
英文描述: 4-Channel E3/DS3/STS-1 Jitter Attenuator,STS-1 to DS3 Desynchronizer(達(dá)到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器)
中文描述: 4通道E3/DS3/STS-1抖動(dòng)衰減器,STS - 1的到DS3 Desynchronizer(達(dá)到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器)
文件頁(yè)數(shù): 12/21頁(yè)
文件大?。?/td> 223K
代理商: XRT71D04
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. P1.0.2
á
PRELIMINARY
11
The XRT71D04 DS3/E3 Jitter Attenuator IC consists
of the following functional blocks:
Timing Control Block
The Jitter-Attenuator PLL
The 2-Channel 16/32 Bit FIFO.
BACKGROUND INFORMATION:
DEFINITION OF JITTER
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as short term
variations of the significant instants of a digita signal
from their ideal positions in time. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
SONET STS-1 to DS3 MAPPING
SONET equipment jitter criteria are specified as:
i) Jitter Transfer
ii) Jitter Tolerance
iii) Jitter Generation
JITTER TRANSFER CHARACTERISTICS:
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 5
F
IGURE
4. I
LLUSTRATION
OF
OF
A
TYPICAL
C
HANNEL
-
N
OF
THE
XRT71D04 (
CONFIGURED
TO
OPERATE
IN
THE
H
OST
M
ODE
)
HOST
RST
16/32 Bit FIFO
Microprocessor Serial
Interface
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRCLKn
RRPOSn
RRNEGn
RRCLKES
FLn
RCLKn
RPOSn
RNEGn
ICT
CS SDI SDO SClk
MClkn
Smoothed
Clock
Jittery
Clock
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