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參數(shù)資料
| 型號： | XRT71D04IVTR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATTENUATOR 4CH 80TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 44.736MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
XRT71D04
á
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
7
49
SDO
O
Serial Data Output:
This pin will serially output the contents of the specified Command Register, dur-
ing “Read” Operations. The data, on this pin, will be updated on the falling edge of
the SCLK input signal. This pin will be tri-stated upon completion of data transfer.
50
DS3/E3_2
I
DS3/E3 Select Input - channel 2:
See description pin 10.
Internal 50 K Ohm pull-down resistor.
51
VDD
****
Digital Power Supply = 5V±5% or 3.3V±5%
52
NC
I
No Connection
53
RCLKES
I
Received Clock Edge Select Input:
Hardware Mode
1. When RCLKES = “0”, then RPOS and RNEG are updated on the falling edge
of RCLK
2. When RCLKES = “1”, then RPOS and RNEG are updated on the rising edge
of RCLK
NOTE: This applies to all channels.
Host Mode
Connect this pin to GND when the 71D04 is configured in the Host Mode.
Internal 50 K Ohm pull-down resistor.
54
NC
No Connection
55
RRNEG_1
O
Received Recovered Negative Data (De-Jittered) Output - channel 1:
See description of pin 6
56
RRPOS_1
O
Received Recovered Positive Data (De-Jittered) Output - channel 1:
See description of pin 5
57
RRCLK_1
O
Received Recovered Output (De-jittered) Clock - channel 1:
See description of pin 4
58
GND
****
Digital Ground
59
NC
No Connection
60
AVDD
****
Analog Power Supply = 5V±5% or 3.3V±5%
61
AGND
****
Analog Ground
62
FL_1
O
FIFO Limit - channel 1:
See description of pin 22
63
STS1_1
I
SONET STS1 Mode Select - channel 1:
See description of pin 23
64
DS3/E3_3
I
DS3/E3 Select Input - channel 3:
See description pin 10.
Internal 50 K Ohm pull-down resistor.
65
DJA_3
I
Disable Jitter Attenuator Input - Channel 3:
See description of pin 25
Internal 50 K Ohm pull-down resistor.
PIN DESCRIPTION
PIN #NAME
TYPE
DESCRIPTION
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