參數(shù)資料
型號: XRT71D03IVTR-F
廠商: Exar Corporation
文件頁數(shù): 1/24頁
文件大?。?/td> 0K
描述: IC JITTER ATTENUATOR 3CH 64TQFP
標準包裝: 1,000
類型: *
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 44.736MHz
除法器/乘法器: 無/無
電源電壓: 3.135 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
SEPTEMBER 2001
REV. 1.2.0
GENERAL DESCRIPTION
The XRT71D03 is a three channel, single chip Jitter
Attenuator, that meets the Jitter transfer characteris-
tics requirements specified in the ETSI TBR-24,
Bellcore GR-499 and GR-253 standards.
In addition, the XRT71D03 also meets the Jitter and
Wander specifications described in the ANSI
T1.105.03b 1997, Bellcore GR-253 and GR-499 stan-
dards.
FEATURES
Meets the E3/DS3/STS-1 jitter requirements
No external components required
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-235-CORE, GR-
499-CORE,1995 standards
Meets output jitter requirement as specified by
ETSI TBR24
Meets the Jitter and Wander specifications
described in T1.105.03b,GR-253 and GR-499 stan-
dards.
Selectable buffer size of 16 and 32 bits
Jitter attenuator can be disabled
Available in a 64 pin LQFP package.
Single 3.3V or 5.0V supply.
Operates over - 40° C to 85° C temperature range.
APPLICATIONS
E3/DS3 Access Equipment.
DSLAMs
FIGURE 1. BLOCK DIAGRAM OF THE XRT71D03
Timing Control Block
Phase locked Loop
RRCLK_n
RRPOS_n
RRNEG_n
FL_n
DJA_n
RClk_n
RClkES
RPOS_n
RNEG_n
FSS
ICT
MCLK_n
STS1_n
DS3/E3_n
Microprocessor Serial
Interface
CS
SDI
SDO SClk
HOST
Reset
Channel 0
Channel 1
Channel 2
XRT71D03
n = 0, 1, 2
MODE_CTRL
Read Clock
Write Clock
16/32 Bit FIFO
RRCLKES
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