參數(shù)資料
型號(hào): XRT7295AEIW
廠(chǎng)商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: E3 (34.368Mbps) Integrated line Receiver
中文描述: DATACOM, PCM TRANSCEIVER, PDSO20
封裝: 0.300 INCH, SOP-20
文件頁(yè)數(shù): 6/15頁(yè)
文件大?。?/td> 861K
代理商: XRT7295AEIW
XRT7295AE
6
Rev. 2.0.0
Line Termination and Input Capacitance
The recommended receive termination is shown in
Figure 3. The 75
resistor terminates the coaxial cable
with its characteristic impedance. The 0.01
μ
F capaci-
tor to R
IN
couples the signal into the receive input
without disturbing the internally generated DC bias
level present on R
IN
. The input capacitance at the R
IN
pin is 2.8pF.
External Loop Filter Capacitor
Figure 3 shows the connection to an external 0.1
μ
F
capacitor at the LPF1/LPF2 pins. This capacitor is part
of the PLL filter. A non-polarized, low-leakage capaci-
tor should be used. A ceramic capacitor with the value
0.1
μ
F +/-20% is acceptable.
Figure 3. Receiver Configuration
TIMING RECOVERY
Output Jitter
The total jitter appearing on the RCLK output during
normal operation consists of two components. First,
some jitter appears on RCLK because of jitter on the
incoming signal. (The following section discussed the
jitter transfer characteristic, which describes the rela-
tionship between input and output jitter.) Second, noise
sources within the XRT7295AE or noise sources that
are coupled into the device through the power supplies
create jitter on RCLK. The magnitude of this
XRT7295AE
XRT7295AE
相關(guān)PDF資料
PDF描述
XRT7295AT DS3/Sonet STS-1 Integrated Line Receiver
XRT7295ATIW DS3/Sonet STS-1 Integrated Line Receiver
XRT7295 ()
XRT7296 INTEGRATED LINE TRANSMITTER
XRT7296IP INTEGRATED LINE TRANSMITTER
相關(guān)代理商/技術(shù)參數(shù)
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