參數(shù)資料
型號(hào): XRT7295AEIW
廠商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: E3 (34.368Mbps) Integrated line Receiver
中文描述: DATACOM, PCM TRANSCEIVER, PDSO20
封裝: 0.300 INCH, SOP-20
文件頁(yè)數(shù): 7/15頁(yè)
文件大?。?/td> 861K
代理商: XRT7295AEIW
XRT7295AE
7
Rev. 2.0.0
internally generated jitter is a function of the PLL
bandwidth, which in turn is a function of the input 1s
density. For higher 1s densities, the amount of gener-
ated jitter decreases. Generated jitter also depends on
the quality of the power supply bypassing networks
used. Figure 8 shows the suggested bypassing net-
work, and Table 3 lists the typical generated jitter
performance achievable with this network.
Figure 4. Pulse Mask at the 34.368 Mbit/s Interface
Parameter
Value
Pulse Shape (Nominally Rectangular)
All marks of a valid signal must conform with the mask
(see Figure 4), irrespective of the sign
Pair(s) in Each Direction
One coaxial pair
Test Load Impedance
75
Resistive
Nominal Peak Voltage of a Mark (Pulse)
1.0V
Peak Voltage of a Space (No Pulse)
0V +/-0.1V
Nominal Pulse Width
14.55ns
Ratio of the Amplitudes of Positive and Negative Pulses
at the Center of a Pulse Interval
0.95 to 1.05
Ratio of the Widths of Positive and Negative Pulses
at the Nominal Half Amplitude
0.95 to 1.05
Table 2. E3 Pulse Specification at the Transmitter Output Port
相關(guān)PDF資料
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XRT7295AT DS3/Sonet STS-1 Integrated Line Receiver
XRT7295ATIW DS3/Sonet STS-1 Integrated Line Receiver
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