XRT73L02M
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
26
When the MTIP_n and MRING_n are connected to the TTIP_n and TRING_n lines, the drive monitor circuit
monitors the line for transitions. The DMO_n (Drive Monitor Output) will be asserted “Low” as long as the tran-
sitions on the line are detected via MTIP_n and MRING_n.
If no transitions on the line are detected for 128 ± 32 TxClk_n periods, the DMO_n output toggles “High” and
when the transitions are detected again, DMO_n toggles “Low”.
N
OTES
:
1.
The Drive Monitor Circuit is only for diagnostic purpose and does not have to be used to operate the transmitter
.
2. With TxMON pin “High”, MTIP and MRING will be internally connected to TTIP and TRING for self-monitoring.
4.0.5
The transmitter section of each channel can either be turned on or off. To turn on the transmitter, set the input
pin TxON to “High” (in Hardware Mode) or in Host Mode set the TxON_n control bits and tie the TxON pins
“High”
When the transmitter is turned off, TTIP_n and TRING_n are tri-stated.
T
RANSMITTER
S
ECTION
O
N
/O
FF
:
N
OTES
:
1. This feature provides support for Redundancy.
2. If configured in Host mode, to permit a system designed for redundancy to quickly shut-off the defective line card
and turn on the back-up line card, setting the TxON_n control bits transfers the control to TxON pins.
5.0
This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the
TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses.
THE RECEIVER SECTION:
5.0.1
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat
losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB.
The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation up
to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the sig-
nal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to gen-
erate Positive and Negative data.
The Equalizer can either be “IN” or “OUT” by setting the REQEN_n pin “High” or “Low” (in Hardware Mode) or
setting the REQEN_n control bit to “1” or “0” (in Host Mode).
AGC/E
QUALIZER
:
R
ECOMMENDATIONS
FOR
E
QUALIZER
S
ETTINGS
:
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/
STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,
the Equalizer can be left “IN” by setting the REQEN_n pin to “High” (in Hardware Mode) or setting the
REQEN_n control bit to “1” (in Host Mode).
However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse
template requirements), it is recommended that the Equalizer be left “OUT” for cable length less than 300 feet
by setting the REQEN_n pin “Low” (in Hardware Mode) or by setting the REQEN_n control bit to “0” (in Host
Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of
better jitter transfer characteristics.
N
OTE
: The results of extensive testing indicates that even when the Equalizer was left “IN” (REQEN_n = “HIGH”),
regardless of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at
Industrial Temperature.