參數(shù)資料
型號: XRT73L03AIV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PQFP120
封裝: 14 X 20 MM, TQFP-120
文件頁數(shù): 30/62頁
文件大小: 494K
代理商: XRT73L03AIV
XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
28
The manner that the LIU handles Dual-Rail data is
described below and illustrated in Figure 15. The
Transmit Section (of a Channel) typically samples the
data on the TPData_(n) and TNData_(n) input pins
on the falling edge of TxClk_(n).
TxClk_(n) is the clock signal that is of the selected
data rate frequency, E3 = 34.368 MHz, DS3 = 44.736
MHz and STS-1 = 51.84 MHz. If the Transmit Section
samples a "1" on the TPData_(n) input pin, then the
Transmit Section of the device ultimately generates a
positive polarity pulse via the TTIP_(n) and TRing_(n)
output pins across a 1:1 transformer. If the Transmit
Section samples a "1" on the TNData_(n) input pin,
then the Transmit Section of the device ultimately
generates a negative polarity pulse via the TTIP_(n)
and TRing_(n) output pins across a 1:1 transformer.
2.1.2
Accepting Single-Rail Data from the Ter-
minal Equipment
To transmit data in a Single-Rail data from the Termi-
nal Equipment, configure the XRT73L03A in the
HOST Mode.
Write a "1" into the TxBin_(n) (TRANSMIT BINary)
bit-field of Command Register CR1-(n) shown below.
N
OTE
:
Please refer to Table 2 for the Address of the indi-
vidual Channel(n).
The Transmit Section of each channel samples this
input pin on the falling edge of the TxClk_(n) clock
signal and encodes this data into the appropriate bi-
polar line signal across the TTIP_(n) and TRing_(n)
output pins.
N
OTES
:
1. In this mode, the Transmit Logic Block ignores the
TNData_(n) input pin.
F
IGURE
14. T
HE
TYPICAL
INTERFACE
FOR
THE
T
RANSMISSION
OF
D
ATA
IN
A
D
UAL
-R
AIL
F
OR
-
MAT
FROM
THE
T
RANSMITTING
T
ERMINAL
E
QUIPMENT
TO
THE
T
RANSMIT
S
ECTION
OF
A
CHANNEL
Exar E3/DS3/STS-1 LIU
Transmit
Logic
Block
TxPOS
TxNEG
TxLineClk
TPData
TNData
TxClk
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
F
IGURE
15. T
HE
XRT73L03A S
AMPLES
THE
DATA
ON
THE
TPD
ATA
AND
TND
ATA
INPUT
PINS
TxClk
TPData
TNData
Data 1 1 0
COMMAND REGISTER CR1-(n)
D4
D3
D2
D1
D0
TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBin_(n)
X
X
X
X
1
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