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參數(shù)資料
| 型號： | XRT73L03AIV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP120 |
| 封裝： | 14 X 20 MM, TQFP-120 |
| 文件頁數(shù)： | 31/62頁 |
| 文件大?。?/td> | 494K |
| 代理商： | XRT73L03AIV |
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
29
2. If the Transmit Section of a given channel is config-
ured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 16 illustrates the behavior of the TPData_(n)
and TxClk_(n) signals when the Transmit Logic Block
has been configured to accept Single-Rail data from
the Terminal Equipment.
2.2
T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IR
-
CUITRY
The on-chip Pulse-Shaping circuitry within the Trans-
mit Section of each Channel in the XRT73L03A gen-
erates pulses of the appropriate shapes and width to
meet the applicable pulse template requirements.
The widths of these output pulses are defined by the
width of the half-period pulses within the TxClk_(n)
signal.
However, if the widths of the pulses within the
TxClk_(n) clock signal are allowed to vary significant-
ly, this could jeopardize the chip’s ability to generate
Transmit Output pulses of the appropriate width and
thereby not meet the Pulse Template requirement
specification. Consequently, the chip’s ability to gen-
erate compliant pulses could depend upon the duty
cycle of the clock signal applied to the TxClk_(n) input
pin.
The Transmit Clock Duty Cycle Adjust Circuitry ac-
cepts clock pulses via the TxClk_(n) input pin at duty
cycles ranging from 30% to 70% and converts them
to a 50% duty cycle.
2.3
T
HE
HDB3/B3ZS E
NCODER
B
LOCK
The purpose of the HDB3/B3ZS Encoder Block is to
aid in the Clock Recovery process at the Remote Ter-
minal Equipment by ensuring an upper limit on the
number of consecutive zeros that can exist within the
line signal.
2.3.1
B3ZS Encoding
If the XRT73L03A has been configured to operate in
the DS3 or SONET STS-1 Modes, then the HDB3/
B3ZS Encoder blocks operate in the B3ZS Mode.
When the Encoder is operating in this mode, it parses
through and searches the Transmit Binary Data
Stream from the Transmit Logic Block for the occur-
rence of three (3) consecutive zeros (e.g., "000"). If
the B3ZS Encoder finds an occurrence of three con-
secutive zeros, then it substitutes these three "0’s",
with either a "00V" or a "B0V" pattern.
Where:
"B" represents a Bipolar pulse that is compliant with
the Alternating Polarity requirements of the AMI (Al-
ternate Mark Inversion) line code; and
"V" represents a Bipolar Violation (e.g., a bipolar
pulse that violates the Alternating Polarity require-
ments of the AMI line code).
The B3ZS Encoder decides whether to substitute
with either the “00V" or the "B0V" pattern in order to
insure that an odd number of bipolar pulses exist be-
tween any two consecutive violation pulses.
Figure 17 illustrates the B3ZS Encoder at work with
two separate strings of three (or more) consecutive
zeros
F
IGURE
16. T
HE
B
EHAVIOR
OF
THE
TPD
ATA
AND
T
X
C
LK
I
NPUT
S
GNALS
,
WHILE
THE
T
RANSMIT
L
OGIC
B
LOCK
IS
A
CCEPTING
S
INGLE
-R
AIL
D
ATA
FROM
THE
T
ERMINAL
E
QUIPMENT
TxClk
TPData
Data 1 1 0
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| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03BIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L03B | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03BES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L03BIV | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L03BIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L03IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
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