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參數(shù)資料
| 型號： | XRT73L03BIV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP120 |
| 封裝： | 14 X 20 MM, LQFP-120 |
| 文件頁數(shù)： | 46/61頁 |
| 文件大?。?/td> | 342K |
| 代理商： | XRT73L03BIV |
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XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
44
channel(n) typically updates the data on the
RPOS_(n) and RNEG_(n) output pins on the rising
edge of RxClk_(n).
RxClk_(n) is the Recovered Clock signal from the in-
coming Received line signal. As a result, these clock
signals are typically 34.368 MHz for E3 applications,
44.736 MHz for DS3 applications and 51.84 MHz for
SONET STS-1 applications.
In general, if a given channel received a positive-po-
larity pulse in the incoming line signal via the
RTIP_(n) and RRing_(n) input pins, then the channel
pulses its corresponding RPOS_(n) output pin “High".
Conversely, if the channel received a negative-polari-
ty pulse in the incoming line signal via the RTIP_(n)
and RRing_(n) input pins, then the channel(n) pulses
its corresponding RNEG_(n) output pin “High".
Inverting the RxClk_(n) outputs
Each channel can invert the RxClk_(n) signals with
respect to the delivery of the RPOS_(n) and
RNEG_(n) output data to the Receiving Terminal
Equipment. This feature may be useful for those cus-
tomers whose Receiving Terminal Equipment logic
design is such that the RPOS_(n) and RNEG_(n) da-
ta must be sampled on the rising edge of RxClk_(n).
Figure 30 illustrates the behavior of the RPOS_(n),
RNEG_(n) and RxClk_(n) signals when the
RxClk_(n) signal has been inverted.
In the Hardware Mode:
Setting the RxClkINV pin “High” results in all chan-
nels of the XRT73L03B to output the recovered data
on RPOS_(n) and RNEG_(n) on the falling edge of
RxClk_(n). Setting this pin “Low” results in the recov-
ered data on RPOS_(n) and RNEG_(n) to output on
the rising edge of RxClk_(n).
a. Operating in the HOST Mode
In order to configure a channel(n) to invert the
RxClk_(n) output signal, the XRT73L03B must be op-
erating in the HOST Mode.
F
IGURE
29. H
OW
THE
XRT73L03B
OUTPUTS
DATA
ON
THE
RPOS
AND
RNEG
OUTPUT
PINS
RxClk
RPOS
RNEG
F
IGURE
30. T
HE
B
EHAVIOR
OF
THE
RPOS, RNEG,
AND
R
X
C
LK
SIGNALS
WHEN
R
X
C
LK
IS
INVERTED
RxClk
RPOS
RNEG
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| XRT73L04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04B | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04BIV | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04 | 4 Channel E3/DS3/STS-1 Line Interface Unit(4通道 E3/DS3/STS-1線接口單元) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L03BIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L03IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| XRT73L03IVS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT73L04A | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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