Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
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PRELIMINARY
XRT73L04
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
SEPTEMBER 2000
REV. P1.0.5
GENERAL DESCRIPTION
The XRT73L04, 4-Channel, DS3/E3/STS-1 Line In-
terface Unit consists of four independent line trans-
mitters and receivers integrated on a single chip de-
signed for DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L04 can be configured to
support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or
the SONET STS-1 (51.84 Mbps) rates. Each channel
can be configured to operate in a mode/data rate that
is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L04 performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Uses Minimum External components
Single +3.3V Power Supply
5V tolerant I/O
-40°C to +85°C Operating Temperature Range
Available in a Thermally Enhanced 144 pin TQFP
package
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
F
IGURE
1. XRT73L04 B
LOCK
D
IAGRAM
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
TxLEV(n)
TxOFF
Channel 2
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
RTIP(n)
RRing(n)
REQEN(n)
Channel 0
Channel 1
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
Device
Monitor
MTIP(n)
MRing(n)
DMO(n)
Transmit
Logic
Duty Cycle Adjust
TTIP(n)
TRing(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3_Ch(n)
STS-1/DS3_Ch(n)
Host/(HW)
RLOL(n)
EXClk(n)
RxOFF
RxClkINV
RxClk(n)
RPOS(n)
RNEG(n)/
(LCV(n))
Channel 3
Tx
Control