參數(shù)資料
型號(hào)： XRT73L04B
廠商： Exar Corporation
英文描述： 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
中文描述： 4通道DS3/E3/STS-1線路接口單元
文件頁數(shù)： 5/64頁
文件大小： 359K
代理商： XRT73L04B
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
II
1.0 SELECTING THE DATA RATE ............................................................................................................... 25
1.1 C
ONFIGURING
C
HANNEL
(
N
) ............................................................................................................ 25
Table 2:Hexadecimal Addresses and Bit Formats of XRT73L04B Command Registers ............................... 26
Table 3:Selecting the Data Rate for Channel(n) via the E3_(n) and STS-1/DS3_(n) input pins (Hardware Mode)
27
C
OMMAND
R
EGISTER
, CR4-(
N
) ........................................................................................................... 27
Table 4:Selecting the Data Rate for Channel(n) via the STS-1/DS3_(n) and the E3_(n) bit-fields within the Ap-
propriate Command Register (HOST Mode) ..................................................................................... 27
2.0 THE TRANSMIT SECTION ...................................................................................................................... 28
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
......................................................................................................... 28
Accepting Dual-Rail Data from the Terminal Equipment ................................................................... 28
Figure 14. The typical interface for the Transmission of Data in a Dual-Rail Format from the Transmitting Ter-
minal Equipment to the Transmit Section of a channel .................................................................... 28
Figure 15.The XRT73L04B Samples the data on the TPData and TNData input pins ................................... 28
Accepting Single-Rail Data from the Terminal Equipment ................................................................ 29
C
OMMAND
R
EGISTER
CR3-(
N
) ............................................................................................................ 29
Figure 16.The Behavior of the TPData and TxClk Input Sgnals, while the Transmit Logic Block is Accepting Sin-
gle-Rail Data from the Terminal Equipment ..................................................................................... 29
2.2 T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IRCUITRY
................................................................. 29
2.3 T
HE
HDB3/B3ZS E
NCODER
B
LOCK
............................................................................................... 29
B3ZS Encoding .................................................................................................................................. 29
Figure 17.An Example of B3ZS Encoding ...................................................................................................... 30
HDB3 Encoding ................................................................................................................................. 30
Figure 18.An Example of HDB3 Encoding ..................................................................................................... 30
Disabling the HDB3/B3ZS Encoder ................................................................................................... 30
C
OMMAND
R
EGISTER
CR3-(
N
) ............................................................................................................ 31
2.4 T
HE
T
RANSMIT
P
ULSE
S
HAPING
C
IRCUITRY
.................................................................................... 31
Figure 19.The Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications .................... 31
Figure 20.The Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ... 32
Enabling the Transmit Line Build-Out Circuit ..................................................................................... 32
C
OMMAND
R
EGISTER
, CR1-(
N
) ........................................................................................................... 32
Disabling the Transmit Line Build-Out Circuit .................................................................................... 32
C
OMMAND
R
EGISTER
, CR1-(
N
) ........................................................................................................... 33
Design Guideline for Setting the Transmit Line Build-Out Circuit ...................................................... 33
The Transmit Line Build-Out Circuit and E3 Applications .................................................................. 33
2.5 I
NTERFACING
THE
T
RANSMIT
S
ECTIONS
OF
THE
XRT73L04B
TO
THE
L
INE
...................................... 33
Figure 21.Recommended Schematic for Interfacing the Transmit Section of the XRT73L04B to the Line .... 33
T
RANSFORMER
R
ECOMMENDATIONS
.................................................................................................... 34
3.0 THE RECEIVE SECTION ......................................................................................................................... 35
3.1 I
NTERFACING
THE
R
ECEIVE
S
ECTIONS
OF
THE
XRT73L04B
TO
THE
L
INE
........................................ 35
Figure 22.Recommended Schematic for Interfacing the Receive Section of the XRT73L04B to the Line (Trans-
former-Coupling) .............................................................................................................................. 35
3.2 T
HE
R
ECEIVE
E
QUALIZER
B
LOCK
................................................................................................... 36
Figure 23.The Typical Application for the System Installer ............................................................................ 36
Guidelines for Setting the Receive Equalizer ................................................................................... 36
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