參數(shù)資料
型號(hào): XRT73L04BIV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁(yè)數(shù): 52/64頁(yè)
文件大小: 359K
代理商: XRT73L04BIV
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
48
b. Operating in the Hardware Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB_(n) input pin (pin
76, 84, 97 or 105) “High" and the RLB_(n) input pin
(pin 77, 85, 96 or 104) "Low".
4.2
T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
.
When a given channel is configured to operate in the
Digital Local Loop-Back Mode, the channel ignores
any signals that are input to the RTIP and RRing in-
put pins. The Transmitting Terminal Equipment trans-
mits clock and data into the XRT73L04B via the TP-
Data, TNData and TxClk input pins. This data is pro-
cessed through the Transmit Clock Duty Cycle Adjust
PLL and the HDB3/B3ZS Encoder block. At this
point, this data is looped back to the HDB3/B3ZS De-
coder block. After this post-Loop-Back data has been
processed through the HDB3/B3ZS Decoder block, it
outputs to the Near-End Receiving Terminal Equip-
ment via the RPOS, RNEG and RxClk output pins.
Figure 34 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
Configure a channel to operate in the Digital Local
Loop-Back Mode by employing either one of the fol-
lowing two-steps:
a. Operating in the Host Mode
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, write a "1" into both the LLB
and RLB bit-fields within Command Register CR4-(n).
COMMAND REGISTER CR4-(n)
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X
STS-1/DS3_(n)
E3_(n)
LLB_(n)
RLB_(n)
X
X
X
1
0
F
IGURE
34. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
PATH
WITHIN
A
GIVEN
CHANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS/(SR/DR)
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1, 2, or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
D4
D3
D2
D1
D0
X
STS-1/DS3_(n)
E3_(n)
LLB_(n) RLB_(n)
X
X
X
1
1
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