參數(shù)資料
型號： XRT73L06
廠商： Exar Corporation
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： 六通道線路接口單元E3/DS3/STS-1
文件頁數(shù)： 4/63頁
文件大?。?/td> 348K
代理商： XRT73L06
XRT73L06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
A
PPLICATIONS
.............................................................................................................................................. 1
Figure 1. Block Diagram of the XRT 73L06 ...................................................................................................... 1
ORDERING INFORMATION ................................................................................................................... 1
F
EATURES
.................................................................................................................................................... 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
...................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
........................................................................................................ 2
Figure 2. XRT73L06 in BGA package (Bottom View) ....................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 8
CONTROL AND ALARM INTERFACE ....................................................................................................... 9
A
NALOG
P
OWER
AND
G
ROUND
................................................................................................................... 12
DIGITAL
P
OWER
AND
G
ROUND
..................................................................................................................... 14
1.0 clock Synthesizer ............................................................................................................................. 16
1.1 C
LOCK
D
ISTRIBUTION
....................................................................................................................................... 16
Figure 4. Clock Distribution Congifured in E3 Mode Without Using SFM ....................................................... 16
Figure 3. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor .......................... 16
2.0 The Receiver Section ....................................................................................................................... 17
Figure 5. Receive Path Block Diagram ........................................................................................................... 17
2.1 R
ECEIVE
L
INE
I
NTERFACE
................................................................................................................................. 17
Figure 6. Receive Line InterfaceConnection ................................................................................................... 17
2.2 A
DAPTIVE
G
AIN
C
ONTROL
(AGC) ..................................................................................................................... 18
2.3 R
ECEIVE
E
QUALIZER
........................................................................................................................................ 18
Figure 7. ACG/Equalizer Blcok Diagram ......................................................................................................... 18
2.3.1 Recommendations for Equalizer Settings ....................................................................................... 18
2.4 C
LOCK
AND
D
ATA
R
ECOVERY
.......................................................................................................................... 18
2.4.1 Data/Clock Recovery Mode ............................................................................................................... 18
2.4.2 Training Mode ..................................................................................................................................... 18
2.5 LOS (L
OSS
OF
S
IGNAL
) D
ETECTOR
.................................................................................................................. 19
2.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 19
2.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 19
T
ABLE
1: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ................................................................... 19
2.5.3 E3 LOS Condition: ............................................................................................................................. 20
Figure 8. Loss Of Signal Definition for E3 as per ITU-T G.775 ....................................................................... 20
Figure 9. Loss of Signal Definition for E3 as per ITU-T G.775. ....................................................................... 20
2.5.4 Interference Tolerance ....................................................................................................................... 21
Figure 10. Interference Margin Test Set up for DS3/STS-1 ............................................................................ 21
Figure 11. Interference Margin Test Set up for E3. ......................................................................................... 21
T
ABLE
2: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
.............................................................................................. 22
2.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 23
2.6 B3ZS/HDB3 D
ECODER
.................................................................................................................................... 23
Figure 12. Receiver Data output and code violation timing ............................................................................ 23
3.0 The Transmitter Section .................................................................................................................. 24
Figure 13. Transmit Path Block Diagram ........................................................................................................ 24
3.1 T
RANSMIT
D
IGITAL
I
NPUT
I
NTERFACE
................................................................................................................ 24
Figure 14. Typical interface between terminal equipment and the XRT73L06 (dual-rail data) ....................... 24
Figure 15. Transmitter Terminal Input Timing ................................................................................................. 25
Figure 16. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 25
3.2 T
RANSMIT
C
LOCK
............................................................................................................................................ 26
3.3 B3ZS/HDB3 E
NCODER
.................................................................................................................................... 26
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