參數(shù)資料
型號: XRT73L06
廠商: Exar Corporation
英文描述: SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: 六通道線路接口單元E3/DS3/STS-1
文件頁數(shù): 52/63頁
文件大?。?/td> 348K
代理商: XRT73L06
XRT73L06
REV. 1.0.2
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
49
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
A
DDRESS
(H
EX
)
T
YPE
R
EGISTER
N
AME
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
0x00
R/W
APS # 1
TxON_n
Table below shows the status of the transmitter based
on the bit and pin setting.
0
0x08
R/W
APS # 2
RxON_n
Set this bit to turn on individual Receiver.
0
0x60
R/W
Interrupt
Enable
INTEN_n
Set this bit to enable the interrupts on per channel
basis.
0
0x61
ROR
Interrupt
Status
INTST_n
Bits are set when an interrupt occurs.The respective
source level interrupt status registers are read to
determine the cause of interrupt.
0
0x62 -
0x6D
Reserved
0x6E
R
Device _ id
Chip_id
This read only register contains device id.
01110110
0x6F
R
Version
Number
Chip_version
This read only register contains chip version number
T
ABLE
17: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
N
R
EGISTERS
(
N
= 0,1,2,3,4,5)
A
DDRESS
(H
EX
)
P
ARAMETER
N
AME
D
ATA
B
ITS
7
6
5
4
3
2
1
0
0x01 (ch 0)
0x11 (ch 1)
0x21 (ch 2)
0x31 (ch 3)
0x41 (ch 4)
0x51 (ch 5)
Interrupt
Enable
(read/write)
Reserved
PRBSER
CNTIE_n
PRBSERI
E_n
Reserved RLOLIE_n RLOSIE_
n
DMOIE_n
0x02 (ch 0)
0x12 (ch 1)
0x22 (ch 2)
0x32 (ch 3)
0x42 (ch 4)
ox52 (ch 5)
Interrupt
Status
(reset on read)
Reserved
PRBSER
CNTIS_n
PRBSERI
S_n
Reserved RLOLIS_n RLOSIS_
n
DMOIS_n
Bit
0
0
Transmitter Status
OFF
OFF
Pin
0
1
1
1
OFF
ON
0
1
相關PDF資料
PDF描述
XRT73L06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73LC00A E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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