參數(shù)資料
型號(hào): XRT73L06IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA217
封裝: 23 X 23 MM, BGA-217
文件頁數(shù): 26/63頁
文件大小: 348K
代理商: XRT73L06IB
XRT73L06
REV. 1.0.2
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
23
2.5.5
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the
internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n
pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to “1”.
Muting the Recovered Data with LOS condition:
N
OTE
:
When the LOS condition is cleared, the recovered data is output on RxPOS_n and RxNEG_n pins.
2.6
The decoder block takes the output from the clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or
contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on
the RLCV_n output pins to indicate line code violation.
B3ZS/HDB3 Decoder
F
IGURE
12. R
ECEIVER
D
ATA
OUTPUT
AND
CODE
VIOLATION
TIMING
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
RxClk
Duty Cycle
45
50
55
%
RxClk Frequency
E3
DS-3
STS-1
34.368
44.736
51.84
MHz
MHz
MHz
t
RRX
RxClk rise time (10% o 90%)
2
4
ns
t
FRX
RxClk falling time (10% to 90%)
2
4
ns
t
CO
RxClk to RPOS/RNEG delay time
4
ns
t
LCVO
RxClk to rising edge of LCV output delay
2.5
ns
RxClk
t
RRX
t
FRX
RPOS or
RNEG
LCV
t
LCVO
t
CO
相關(guān)PDF資料
PDF描述
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