參數(shù)資料
型號: XRT73R06IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA217
封裝: 23 X 23 MM, BGA-217
文件頁數(shù): 35/68頁
文件大小: 347K
代理商: XRT73R06IB
á
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73R06
REV. 1.0.0
32
4.5
4.5.1
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLOS condition occurs, the DLOS_n bit is set to “1” in the status control register. DLOS condition is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses. Analog Loss of
Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown
in the Table 6.The status of the ALOS condition is reflected in the ALOS_n status control register. RLOS is the
logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled
“High” and the RLOS_n bit is set to “1” in the status control register.
LOS (Loss of Signal) Detector
DS3/STS-1 LOS Condition
4.5.2
For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a “1” to both
ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis.
Disabling ALOS/DLOS Detection
T
ABLE
6: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
)
A
PPLICATION
REQEN S
ETTING
LOSTHR S
ETTING
S
IGNAL
L
EVEL
TO
D
ECLARE
ALOS
D
EFECT
S
IGNAL
L
EVEL
TO
C
LEAR
ALOS
D
EFECT
DS3
0
0
< 75mVpk
> 130mVpk
1
0
< 45mVpk
> 60mVpk
0
1
< 120mVpk
> 45mVpk
1
1
< 55mVpk
> 180mVpk
STS-1
0
0
< 120mVpk
> 170mVpk
1
0
< 50mVpk
> 75mVpk
0
1
< 125mVpk
> 205mVpk
1
1
< 55mVpk
> 90mVpk
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