- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9992 > XRT75L03DIVTR-F (Exar Corporation)IC LIU E3/DS3/STS-1 3CH 128LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT75L03DIVTR-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 129/134頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)當(dāng)前第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)
XRT75L03D
á
REV. 1.0.0
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
89
9.0
THE SONET/SDH DE-SYNC FUNCTION WITHIN THE XRT75L03D
The XRT75L03D LIU IC is very similar to the XRT75L03 in that they are both 3-Channel DS3/E3/STS-1 LIU
devices that also contain Jitter Attenuator blocks within each of the three channels. They are also pin to pin
compatible with each other. However, the Jitter Attenuators within the XRT75L03D has some enhancements
over and above those within the XRT75L03 (non-D) device. The Jitter Attenuator blocks within the XRT75L03D
will support all of the modes and features that exist in the XRT75L03 (non-D) device and in addition they also
support a SONET/SDH De-Sync Mode not available within the XRT75L03D.
NOTE: The "D" suffix within the part number, XRT75L03D stands for "De-Sync".
The SONET/SDH De-Sync feature of the Jitter Attenuator blocks in the XRT75L03D permits the user to design
a SONET/SDH PTE (Path Terminating Equipment) that will comply with all of the following Intrinsic Jitter and
Wander requirements.
For SONET Applications
s
Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 Applications)
s
ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
For SDH Applications
s
Jitter and Wander Generation Requirements per ITU-T G.783 (for DS3 and E3 Applications)
Specifically, if the user designs in the XRT75L03D
along with a SONET/SDH Mapper IC (which can be
realized as either a standard product or as a custom logic solution, in an ASIC or FPGA), then the followind can
be accomplished;
The Mapper can receive an STS-N or an STM-M signal (which is carrying asynchronously-mapped DS3 and/
or E3 signals) and byte de-interleave this data into N STS-1 or 3*M VC-3 signals
The Mapper will then terminate these STS-1 or VC-3 signals and will de-map out this DS3 or E3 data from
the incoming STS-1 SPEs or VC-3s, and output this DS3 or E3 to the DS3/E3 Facility-side towards the
XRT75L03D
This DS3 or E3 signal (as it is output from these Mapper devices) will contain a large amount intrinsic jitter
and wander due to (1) the process of asynchronously mapping a DS3 or E3 signal into a SONET or SDH
signal, (2) the occurrence of Pointer Adjustments within the SONET or SDH signal (transporting these DS3
or E3 signals) as it traverses the SONET/SDH network, and (3) clock gapping.
When the XRT75L03D has been configured to operate in the "SONET/SDH De-Sync" Mode, then it will (1)
accept this jittery DS3 or E3 clock and data signal from the Mapper device (via the Transmit System-side
interface) and (2) through the Jitter Attenuator, the XRT75L03D will reduce the Jitter and Wander amplitude
within these DS3 or E3 signals such that they (when output onto the line) will comply with the above-
mentioned intrinsic jitter and wander specifications.
9.1
BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS
This section provides an in-depth discussion on the mechanisms that will cause Jitter and Wander within a
DS3 or E3 signal that is being transported across a SONET or SDH Network.
A lot of this material is
introductory, and can be skipped by the engineer that is already experienced in SONET/SDH designs. In this
case, the user should proceed directly to “Section 9.8, Designing with the XRT75L03D” on page 118, which
describes how to configure the XRT75L03D in the appropriate set of modes in order to support this application.
In the wide-area network (WAN) in North America it is often necessary to transport a DS3 signal over a long
distance (perhaps over a thousand miles) in order to support a particular service. Now rather than realizing
this transport of DS3 data, by using over a thousand miles of coaxial cable (interspaced by a large number of
DS3 repeaters) a common thing to do is to route this DS3 signal to a piece of equipment (such as a Terminal
MUX, which in the "SONET Community" is known as a PTE or Path Terminating Equipment). This Terminal
MUX will asynchronously map the DS3 signal into a SONET signal. At this point, the SONET network will now
transport this asynchronously mapped DS3 signal from one PTE to another PTE (which is located at the other
end of the SONET network). Once this SONET signal arrives at the remote PTE, this DS3 signal will then be
extracted from the SONET signal, and will be output to some other DS3 Terminal Equipment for further
processing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72835LB15PF | IC FIFO SYNC DL 2048X18 128TQFP |
| XRT75L06IB | IC LIU E3/DS3/STS-1 6CH 217BGA |
| ISL26132AVZ-T | IC ADC 24BIT SRL 80SPS 24TSSOP |
| VI-21R-MX-F2 | CONVERTER MOD DC/DC 7.5V 75W |
| VI-23W-IU-F1 | CONVERTER MOD DC/DC 5.5V 200W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75L03ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3 CH T3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75L03IV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3CH E3/DS3/STS1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75L03IV-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75L03IVTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CH E3/DS3/STS1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75L03IVTR-F | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。