參數(shù)資料
型號： XRT75L03IVTR-F
廠商： Exar Corporation
文件頁數(shù)： 12/92頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 3CH 128LQFP
標(biāo)準(zhǔn)包裝： 750
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 3/3
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 帶卷 (TR)
XRT75L03
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
2
TRANSMIT INTERFACE CHARACTERISTICS
Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
Integrated Pulse Shaping Circuit
Built-in B3ZS/HDB3 Encoder (which can be disabled)
Accepts Transmit Clock with duty cycle of 30%-70%
Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications
Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
ANSI T1.102_1993
Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE
Transmitter can be turned off in order to support redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
Integrated Adaptive Receive Equalization (optional) for optimal Clock and Data Recovery
Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications
Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications
Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications
Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms
Built-in B3ZS/HDB3 Decoder (which can be disabled)
Recovered Data can be muted while the LOS Condition is declared
Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L03
HOST/HW
STS-1/DS3_(n)
E3_(n)
REQEN_(n)
RTIP_(n)
RRing_(n)
SR/DR
XRT75L03
RLB_(n)
RLOS_(n)
JATx/Rx
TPData_(n)
TNData_(n)
TxClk_(n)
TAOS_(n)
TxLEV_(n)
TxON_(n)
Channel 2
Channel 0
Channel 1
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in "Host" Mode and redefined in the "Hardware" Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Timing
Control
TTIP_(n)
TRing_(n)
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
RLOL_(n)
RxON
RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)/
LCV_(n)
Tx
Control
Jitter
Attenuator
MUX
Line
Driver
LOSTHR
LLB_(n)
Invert
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
Jitter
Attenuator
Serial
Processor
Interface
Local
LoopBack
Clock & Data
Recovery
Clock
Synthesizer
E3Clk,DS3Clk,
STS-1Clk
RESET
CS
SClk
INT
SDO
SDI
CLKOUT
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