參數(shù)資料
型號(hào): XRT75L03IVTR-F
廠商: Exar Corporation
文件頁數(shù): 2/92頁
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
標(biāo)準(zhǔn)包裝: 750
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 帶卷 (TR)
XRT75L03
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
7
40
127
22
DMO_0
DMO_1
DMO_2
O
Drive Monitor Output - Channel 0:
Drive Monitor Output - Channel 1:
Drive Monitor Output - Channel 2:
These output signals are used to indicate some sort of fault condition within
the Transmit Output signal path.
This output pin will toggle "High" anytime the Transmit Drive Monitor cir-
cuitry either, via the corresponding MTIP and MRING input pins or inter-
nally, detects no bipolar pulses via the Transmit Output line signal (e.g., via
the TTIP_n and TRING_n output pins) for 128 bit-periods.
This output pin will be driven "Low" anytime the Transmit Drive Monitor cir-
cuitry has detected at least one bipolar pulse via the Transmit Output line
signal within the last 128 bit periods.
67
TxClkINV/
SClk
I
Hardware Mode: Transmit Clock Invert
Host Mode: Serial Clock Input:
Hardware mode
This input pin is used to select the edge of the TxCLK_n input that the
Transmit Section of all channels will use to sample the TPDATA_n and
TNDATA_n input pins.
Setting this input pin “High” configures all three Transmitters to sample the
TPData_n and TNData_n data on the rising edge of the TxClk_n .
Setting this input pin “Low” configures all three Transmitters to sample the
TPData_n and TNData_n data on the falling edge of the TxClk_n .
Host Mode
In the Host Mode this pin functions as SClk input pin please refer to the pin
descriptions for the Microprocessor interface.
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN #SIGNAL NAME
TYPE
DESCRIPTION
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