JITTER <" />
參數(shù)資料
型號: XRT75L06DIB-F
廠商: Exar Corporation
文件頁數(shù): 39/103頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 6CH 217BGA
標準包裝: 60
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 6/6
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 217-BBGA
供應商設(shè)備封裝: 217-BGA(23x23)
包裝: 托盤
XRT75L06D
xr
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.4
36
4.2
JITTER TRANSFER
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as
the highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a
low bandwidth loop, typically using a voltage-controlled crystal oscillator (VCXO).
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter. Table 9
shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
NOTE: The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
4.3
Jitter Attenuator
An advanced crystal-less jitter attenuator per channel is included in the XRT75L06D. The jitter attenuator
requires no external crystal nor high-frequency reference clock. By clearing or setting the JATx/Rx_n bits in
the channel control registers selects the jitter attenuator either in the Receive or Transmit path on per channel
basis. The FIFO size can be either 16-bit or 32-bit. The bits JA0_n and JA1_n can be set to appropriate
combination to select the different FIFO sizes or to disable the Jitter Attenuator on a per channel basis. Data is
clocked into the FIFO with the associated clock signal (TxClk or RxClk) and clocked out of the FIFO with the
dejittered clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL_n
is set to “1” in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter. Table 10 specifies the jitter transfer mask requirements for various data rates:
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
BIT RATE
(KB/S)
STANDARD
INPUT JITTER AMPLITUDE (UI
P
-P)
MODULATION FREQUENCY
A1
A2
A3
F
1(HZ)
F
2(HZ)
F
3(KHZ)
F
4(KHZ)
F
5(KHZ)
34368
ITU-T G.823
1.5
0.15
-
100
1000
10
800
-
44736
GR-499
CORE Cat I
5
0.1
-
10
2.3k
60
300
-
44736
GR-499
CORE Cat II
10
0.3
-
10
669
22.3
300
-
51840
GR-253
CORE Cat II
15
1.5
0.15
10
30
300
2
20
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES
E3
DS3
STS-1
ETSI TBR-24
GR-499 CORE section 7.3.2
Category I and Category II
GR-253 CORE section 5.6.2.1
相關(guān)PDF資料
PDF描述
XRT75L06IB-F IC LIU E3/DS3/STS-1 6CH 217BGA
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XRT75R03 制造商:EXAR 制造商全稱:EXAR 功能描述:THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03D 制造商:EXAR 制造商全稱:EXAR 功能描述:THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER