參數(shù)資料
型號(hào)： XRT75R03
廠商： Exar Corporation
英文描述： THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述： Three頻道E3/DS3/STS-1線路接口單元與抖動(dòng)衰減器
文件頁數(shù)： 5/92頁
文件大小： 492K
代理商： XRT75R03
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03
REV. 1.0.7
II
6.0 THE RECEIVER SECTION: .................................................................................................................43
6.1 AGC/EQUALIZER: .......................................................................................................................................... 43
6.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 44
F
IGURE
18. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
DS3/STS-1................................................................................................ 44
F
IGURE
19. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
E3. ............................................................................................................ 45
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
........................................................................................................................... 45
6.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 45
6.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 46
6.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 46
6.4.1 DS3/STS-1 LOS CONDITION:.................................................................................................................................... 46
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
)............................................................................................................................................. 46
D
ISABLING
ALOS/DLOS D
ETECTION
: ..........................................................................................................46
6.4.2 E3 LOS CONDITION:.................................................................................................................................................. 46
F
IGURE
20. L
OSS
O
F
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775.......................................................................................... 47
F
IGURE
21. L
OSS
OF
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775. ......................................................................................... 47
6.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 48
7.0 JITTER: ................................................................................................................................................48
7.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 48
F
IGURE
22. J
ITTER
T
OLERANCE
M
EASUREMENTS
........................................................................................................................... 48
7.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 48
F
IGURE
23. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1................................................................................................................ 49
7.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 49
F
IGURE
24. I
NPUT
J
ITTER
T
OLERANCE
FOR
E3.............................................................................................................................. 49
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) .................................................................. 50
7.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 50
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
............................................................................................................ 50
7.3 JITTER ATTENUATOR: ................................................................................................................................. 50
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
.................................................................................................................................... 51
F
IGURE
25. J
ITTER
T
RANSFER
R
EQUIREMENTS
AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
................................................................ 51
7.3.1 JITTER GENERATION: .............................................................................................................................................. 51
8.0 SERIAL HOST INTERFACE: ...............................................................................................................51
T
ABLE
14: F
UNCTIONS
OF
SHARED
PINS
......................................................................................................................................... 52
T
ABLE
15: XRT75R03 R
EGISTER
M
AP
- Q
UICK
L
OOK
.................................................................................................................... 53
Legend: ..................................................................................................................................................................... 56
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75R03 3-CHANNEL DS3/E3/STS-1 LIU IC 56
T
ABLE
16: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT75R03 3-C
HANNEL
DS3/E3/STS-1 LIU
W
/ J
ITTER
A
TTENUATOR
IC56
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................58
T
ABLE
17: L
IST
AND
A
DDRESS
L
OCATIONS
OF
G
LOBAL
R
EGISTERS
................................................................................................. 58
REGISTER DESCRIPTION - GLOBAL REGISTERS ...............................................................................58
T
ABLE
18: APS/R
EDUNDANCY
C
ONTROL
R
EGISTER
- CR0 (A
DDRESS
L
OCATION
= 0
X
00)............................................................... 58
T
ABLE
19: B
LOCK
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR32 (A
DDRESS
L
OCATION
= 0
X
20)....................................................... 61
T
ABLE
20: B
LOCK
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR33 (A
DDRESS
L
OCATION
= 0
X
21)....................................................... 62
T
ABLE
21: D
EVICE
/P
ART
N
UMBER
R
EGISTER
- CR62 (A
DDRESS
L
OCATION
= 0
X
3E)....................................................................... 63
T
ABLE
22: C
HIP
R
EVISION
N
UMBER
R
EGISTER
- CR63 (A
DDRESS
L
OCATION
= 0
X
3F)..................................................................... 64
THE PER-CHANNEL REGISTERS...........................................................................................................64
T
ABLE
23: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT75R03 3-C
HANNEL
DS3/E3/STS-1 LIU
W
/ J
ITTER
A
TTENUATOR
IC64
REGISTER DESCRIPTION - PER CHANNEL REGISTERS....................................................................66
T
ABLE
24: S
OURCE
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
01 .............................................. 66
T
ABLE
25: S
OURCE
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
02 .............................................. 68
T
ABLE
26: A
LARM
S
TATUS
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
03............................................................................. 70
T
ABLE
27: T
RANSMIT
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
04 ..................................................................... 75
T
ABLE
28: R
ECEIVE
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
05 ....................................................................... 78
T
ABLE
29: C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06...................................................................... 80
T
ABLE
30: J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07 ..................................................... 83
9.0 DIAGNOSTIC FEATURES: .................................................................................................................84
9.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 84
F
IGURE
26. PRBS MODE............................................................................................................................................................. 84
9.2 LOOPBACKS: ................................................................................................................................................ 84
9.2.1 ANALOG LOOPBACK:............................................................................................................................................... 84
F
IGURE
27. A
NALOG
L
OOPBACK
..................................................................................................................................................... 85
9.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 86
F
IGURE
28. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 86
相關(guān)PDF資料
PDF描述
XRT75R03IV THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R03D 制造商:EXAR 制造商全稱:EXAR 功能描述:THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
XRT75R03D_06 制造商:EXAR 制造商全稱:EXAR 功能描述:EXAR DATA SHEET FORMAT TEMPLATES
XRT75R03DES 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CH T3/E3/STS1LIU+D 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R03DIV 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R03DIV-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3-Ch E3/DS3/STS-1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*