參數(shù)資料
型號： XRT75R03D
廠商： Exar Corporation
英文描述： THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
中文描述： Three頻道E3/DS3/STS-1線路接口單元與SONET DESYNCRONIZER
文件頁數(shù)： 5/134頁
文件大小： 803K
代理商： XRT75R03D
XRT75R03D
REV. 1.0.2
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER
II
Figure 15. B3ZS Encoding Format ................................................................................................................. 42
Figure 16. HDB3 Encoding Format ................................................................................................................ 42
5.3 T
RANSMIT
P
ULSE
S
HAPER
: .............................................................................................................................. 43
5.3.1 Guidelines for using Transmit Build Out Circuit: ........................................................................... 43
5.3.2 Interfacing to the line: ....................................................................................................................... 43
5.4 T
RANSMIT
D
RIVE
M
ONITOR
: ............................................................................................................................. 44
5.5 T
RANSMITTER
S
ECTION
O
N
/O
FF
: ...................................................................................................................... 44
6.0 The Receiver Section: ...................................................................................................................... 44
6.1 AGC/E
QUALIZER
: ............................................................................................................................................ 44
Figure 17. Transmit Driver Monitor set-up. ..................................................................................................... 44
6.1.1 Interference Tolerance: ..................................................................................................................... 45
Figure 18. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 45
6.2 C
LOCK
AND
D
ATA
R
ECOVERY
: ......................................................................................................................... 46
Figure 19. Interference Margin Test Set up for E3. ........................................................................................ 46
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
.............................................................................................. 46
6.3 B3ZS/HDB3 D
ECODER
: .................................................................................................................................. 47
6.4 LOS (L
OSS
OF
S
IGNAL
) D
ETECTOR
: ................................................................................................................ 47
6.4.1 DS3/STS-1 LOS Condition: ................................................................................................................ 47
D
ISABLING
ALOS/DLOS D
ETECTION
: ......................................................................................................... 47
6.4.2 E3 LOS Condition: ............................................................................................................................. 47
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ................................................................... 47
Figure 20. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 48
Figure 21. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 48
6.4.3 Muting the Recovered Data with LOS condition: ............................................................................ 49
7.0 Jitter: ................................................................................................................................................. 49
7.1 J
ITTER
T
OLERANCE
- R
ECEIVER
: ...................................................................................................................... 49
7.1.1 DS3/STS-1 Jitter Tolerance Requirements: ..................................................................................... 49
Figure 22. Jitter Tolerance Measurements ..................................................................................................... 49
7.1.2 E3 Jitter Tolerance Requirements: ................................................................................................... 50
Figure 23. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 50
Figure 24. Input Jitter Tolerance for E3 ......................................................................................................... 50
7.2 J
ITTER
T
RANSFER
- R
ECEIVER
/T
RANSMITTER
: .................................................................................................. 51
7.3 J
ITTER
A
TTENUATOR
: ...................................................................................................................................... 51
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ..................................... 51
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
............................................................................... 51
7.3.1 Jitter Generation: ............................................................................................................................... 52
8.0 Serial Host interface: ....................................................................................................................... 52
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
....................................................................................................... 52
Figure 25. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 52
T
ABLE
14: F
UNCTIONS
OF
SHARED
PINS
............................................................................................................ 53
T
ABLE
15: XRT75R03D R
EGISTER
M
AP
- Q
UICK
L
OOK
.................................................................................... 54
................................................................................................................................................................. 56
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU IC .
56
Legend: ..................................................................................................................................................................56
T
ABLE
16: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT75R03D 3-C
HANNEL
DS3/E3/STS-1 LIU
W
/ J
ITTER
A
TTENUATOR
IC ................................................................................................................................. 56
THE GLOBAL/CHIP-LEVEL REGISTERS ............................................................................................... 58
................................................................................................................................................................. 58
REGISTER DESCRIPTION - GLOBAL REGISTERS .............................................................................. 58
T
ABLE
17: L
IST
AND
A
DDRESS
L
OCATIONS
OF
G
LOBAL
R
EGISTERS
.................................................................... 58
T
ABLE
18: APS/R
EDUNDANCY
C
ONTROL
R
EGISTER
- CR0 (A
DDRESS
L
OCATION
= 0
X
00) .................................. 58
T
ABLE
19: B
LOCK
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR32 (A
DDRESS
L
OCATION
= 0
X
20) ......................... 61
T
ABLE
20: B
LOCK
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR33 (A
DDRESS
L
OCATION
= 0
X
21) ......................... 62
T
ABLE
21: D
EVICE
/P
ART
N
UMBER
R
EGISTER
- CR62 (A
DDRESS
L
OCATION
= 0
X
3E) .......................................... 63
................................................................................................................................................................. 64
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R03D_06 制造商:EXAR 制造商全稱:EXAR 功能描述:EXAR DATA SHEET FORMAT TEMPLATES
XRT75R03DES 功能描述:時鐘合成器/抖動清除器 3CH T3/E3/STS1LIU+D 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R03DIV 功能描述:時鐘合成器/抖動清除器 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R03DIV-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3-Ch E3/DS3/STS-1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R03DIVTR 功能描述:時鐘合成器/抖動清除器 3CHNNEL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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