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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | XRT75R12IB-L |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 63/90闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 40 |
| 椤炲瀷锛� | 绶氳矾鎺ュ彛瑁濈疆锛圠IU锛� |
| 椹�(q奴)鍕曞櫒/鎺ユ敹鍣ㄦ暩(sh霉)锛� | 12/12 |
| 瑕�(gu墨)绋嬶細 | DS3锛孍3锛孲TS-1 |
| 闆绘簮闆诲锛� | 3.135 V ~ 3.465 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 420-LBGA 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 420-TBGA锛�35x35锛� |
| 鍖呰锛� | 鎵樼洡 |
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XRT75R12
63
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 26: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR225 (ADDRESS LOCATION = 0XE1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved Reserved
Channel 11
Interrupt Status
Channel 10
Interrupt Status
Channel 9
Interrupt Status
Channel 8
Interrupt Status
Channel 7
Interrupt Status
Channel 6
Interrupt Status
R/O
BIT
NUMBER
NAME
TYPE
DESCRIPTION
7, 6
Reserved
5
4
3
2
1
0
Channel 11 Interrupt Status
Channel 10 Interrupt Status
Channel 9 Interrupt Status
Channel 8 Interrupt Status
Channel 7 Interrupt Status
Channel 6 Interrupt Status
R/O
Channel n Interrupt Status Bit:
This READ-ONLY bit-field indicates whether the XRT75R12 has a
pending Channel n-related interrupt that is awaiting service. The last
six channels are serviced through this location and the other six at
address 0x61. These two registers are used by the Host to identify the
source channel of an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting ser-
vice.
1 - Indicates that there is at least one Channel n-related Interrupt await-
ing service. In this case, the user's Interrupt Service routine should be
written such that the Microprocessor will now proceed to read out the
contents of the Source Level Interrupt Status Register - Channel n
(Address Locations = 0xn2) to determine the exact source of the inter-
rupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to "0"
until the user has read out the contents of the Source-Level
Interrupt Status Register bit, that corresponds to the interrupt
request channel.
TABLE 27: DEVICE/PART NUMBER REGISTER - CR110 (ADDRESS LOCATION = 0X6E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Part Number ID Value
R/O
0
1
0
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
7 - 0
Part Number ID
Value
R/O
0x78
Part Number ID Value:
This READ-ONLY register contains a unique value for the
XRT75R12. This value will always be 0x78.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| XRT75VL00DIV | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT75VL00IV-F | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT79L71IB-F | IC LIU/FRAMER DS3/E3 1CH 208BGA |
| XRT81L27IV-F | IC LIU EI 7CH 3.3V 128TQFP |
| XRT82D20IW-F | IC LIU E1 SGL 28SOJ |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| XRT75VL00 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75VL00_08 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75VL00D | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75VL00D_08 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET |
| XRT75VL00D1V-F | 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪: |
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