參數(shù)資料
型號: XRT75VL00IV
廠商: Exar Corporation
文件頁數(shù): 32/50頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 1CH 52TQFP
標(biāo)準(zhǔn)包裝: 96
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應(yīng)商設(shè)備封裝: 52-TQFP(10x10)
包裝: 托盤
XRT75VL00
36
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.6
clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL is set to “1”
in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter.
Table 13 specifies the jitter transfer mask requirements for various data rates:
The jitter attenuator within the XRT75VL00 meets the latest jitter attenuation specifications and/or jitter transfer
characteristics as shown in the Figure 24.
TABLE 13: JITTER TRANSFER PASS MASKS
RATE
(KBITS)
MASK
F1
(HZ)
F2
(HZ)
F3
(HZ)
F4
(KHZ)
A1(dB)
A2(dB)
34368
G.823
ETSI-TBR-24
100
300
3K
800K
0.5
-19.5
44736
GR-499, Cat I
GR-499, Cat II
GR-253 CORE
10
10k
56.6k
40
-
15k
300k
15k
0.1
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
F 1
A 1
F 2
J
IT
T
E
R
A
M
P
L
IT
U
D
E
J IT T E R F R E Q U E N C Y (k H z )
A 2
F 3
F 4
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