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參數(shù)資料
| 型號： | XRT75VL00IV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 49/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-TQFP（10x10） |
| 包裝： | 托盤 |
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XRT75VL00
6
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.6
RECEIVE INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
25
RxON/
SDI
I
Receiver Turn ON Input or Serial Data Input:
Function of this pin depends on whether the XRT75VL00 is configured to oper-
ate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” turns on and enables the
Receiver..
NOTES:
1.
If the XRT75VL00 is configured in HOST mode, this pin functions as
SDI input pin (please refer to the pin description for Microprocessor
Interface)
2.
This pin is internally pulled down.
23
REQEN
I
Receive Equalization Enable Input
Setting this input pin "High" enables the Internal Receive Equalizer. Setting this
pin "Low" disables the Internal Receive Equalizer.
NOTES:
1.
This input pin is ignored and may be connected to GND if the
XRT75VL00 is operating in the HOST Mode
2.
36
RxClk
O
Receive Clock Output
The Recovered Clock signal from the incoming line signal is output through this
pin.By default, the Receiver Section outputs data via RPOS and RNEG pins on
the rising edge of this clock signal.
Configure the Receiver Section to update data on the RPOS and RNEG pins on
the falling edge of RxClk by doing the following:
a) Operating in Hardware mode, pull the RxClkINV pin to “High”.
b) Operating in Host mode, write a “1” to RxClkINV bit field within the Receive
Control Register.
24
RxClkINV/
CS
I
RxClk INVERT or Chip Select:
Function of this pin depends on whether the XRT75VL00 is configured to oper-
ate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Receiver Sec-
tion
to invert the RxClk output signals and outputs the recovered data via
RPOS and RNEG on the falling edge of RxClk.
NOTE: If the XRT75VL00 is configured in HOST mode, this pin functions as CS
input pin (please refer to the pin description for Microprocessor
Interface).
38
RPOS
O
Receive Positive Data Output
This output pin pulses “High" whenever the XRT75VL00 has received a Positive
Polarity pulse in the incoming line signal at the RTIP/RRing inputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75VL00IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75VL00IVTR | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75VL00IVTR-F | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT79L71 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - |
| XRT79L71_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE |
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