JITTER
參數(shù)資料
型號(hào)： XRT75VL00IVTR
廠(chǎng)商： Exar Corporation
文件頁(yè)數(shù)： 31/50頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 1CH 52TQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 線(xiàn)路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 52-LQFP
供應(yīng)商設(shè)備封裝： 52-TQFP（10x10）
包裝： 帶卷 (TR)
XRT75VL00
35
REV. 1.0.6
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
6.2
JITTER TRANSFER - RECEIVER/TRANSMITTER:
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency.
There are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio
above 0 dB; and jitter transfer bandwidth.The overall jitter transfer bandwidth is controller by a low bandwidth
loop,which is part of the XRT75VL00..
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter.A zero dB jitter transfer indicates the element had no effect on jitter.
Table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
The XRT75VL00 meets the above Jitter Specifications.
6.3
JITTER GENERATION:
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and
data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is
essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set
according to the data rate. In general, the jitter is measured over a band of frequencies.
6.4
Jitter Attenuator:
An advanced crystal-less jitter attenuator is included in the XRT75VL00. The jitter attenuator uses the internal
reference clock.
In Host mode, by clearing or setting the JATx/Rx bit in the control register selects the jitter attenuator either in
the Receive or Transmit path. In Hardware mode, JATx/Rx pin selects the jitter attenuator in Receive or
Transmit path.
The FIFO is either a 16-bit or 32-bit register. In Host mode, the bits JA0 and JA1can be set to appropriate
combination to select the different FIFO sizes or to disable the jitter attenuator. In Hardware mode, appropriate
setting of the pins JA0 and JA1 selects the different FIFO sizes or disable the jitter attenuator. Data is clocked
into the FIFO with the associated clock signal (TxClk or RxClk) and clocked out of the FIFO with the dejittered
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
BIT RATE
(KB/S)
STANDARD
INPUT JITTER AMPLITUDE (UI
P
-P)
MODULATION FREQUENCY
A1
A2
A3
F
1(HZ)
F
2(HZ)
F
3(KHZ)
F
4(KHZ)
F
5(KHZ)
34368
ITU-T G.823
1.5
0.15
-
100
1000
10
800
-
44736
GR-499
CORE Cat I
5
0.1
-
10
2.3k
60
300
-
44736
GR-499
CORE Cat II
10
0.3
-
10
669
22.3
300
-
51840
GR-253
CORE Cat II
15
1.5
0.15
10
30
300
2
20
TABLE 12: JITTER TRANSFER SPECIFICATIONS
E3
DS3
STS-1
ETSI TBR-24
GR-499 CORE section 7.3.2
Category I and Category II
GR-253 CORE section 5.6.2.1
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