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參數(shù)資料
| 型號(hào)： | XRT82L24AIV-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 38/39頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU E1 QAUD 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | E1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | XRT82L24AIV-F-ND |
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XRT82L24A
á
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
6
8
PTS2
SR/DR
I
Host Mode:
Processor Type Select Input bit 2:
See description for pin 7.
Hardware Mode
Single rail/Dual Rail Control
Connect this pin “Low” to select transmit and receive data format in dual-rail
mode. In this mode, HDB3 encoder and decoder are not available. Connect this
pin "High" to select single-rail data format.
NOTE: Internally pulled -downwith a 50k
resistor.
9
HW/HOST
I
Mode Control Input:
This pin is used to select the operating mode of the device, (Hardware Mode or
Host Mode.)
In Hardware Mode, the parallel Microprocessor interface is disabled and
enables all hardware control pin functions.
In Host Mode, the parallel microprocessor interface pins are used for control
functions.
NOTE: Internally pulled "High" with 50k
.
10
PCLK
Codes
I
Processor Clock Input.
Input clock for synchronous microprocessor operation. Maximum clock rate is
16 MHz. This pin is internally pulled-up for asynchronous microprocessor inter-
face when no clock is present.
Coding/Decoding Select.
In Hardware Mode, if single-rail data format is selected (pin 8 =”1”), connect
this pin "High" to select AMI encoding and decoding. Connect this pin Low to
select HDB3.
14
WR_R/W
I
Write Input (Read/Write).
With Intel bus timing, a Low pulse on WR selects a write operation when CS pin
is Low. When configured in Motorola bus timing, a "High" pulse on R/W selects
a read operation and a Low pulse on R/W selects a write operation when CS is
Low.
15
RD_DS
I
Read Input (Data Strobe).
With Intel bus timing, a Low pulse on RD selects a read operation when CS pin
is Low. When configured in Motorola bus timing, a Low pulse on DS indicates a
read or write operation when CS pin is Low.
16
ALE_AS
I
Address Latch Input (Address Strobe).
With Intel bus timing, the address inputs are latched into the internal register on
the falling edge of ALE. When configured in Motorola bus timing, the address
inputs are latched into the internal register on the falling edge of AS.
17
CS
I
Chip Select Input.
This signal must be Low in order to access the parallel port.
PIN DESCRIPTIONS
PIN #NAME
TYPE
DESCRIPTION
Pin 9
Operating Mode
“Low”
Host Mode
“High”
Hardware Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L24ES | 功能描述:界面開發(fā)工具 Evaluation Board for XRT82L24 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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