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參數(shù)資料
| 型號： | XRT82L34 |
| 廠商： | Exar Corporation |
| 英文描述： | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）) |
| 中文描述： | 四路T1/E1/J1收發(fā)線收發(fā)器時(shí)鐘恢復(fù)和抖動(dòng)衰減器（四的T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）） |
| 文件頁數(shù)： | 1/50頁 |
| 文件大?。?/td> | 648K |
| 代理商： | XRT82L34 |
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Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
á
PRELIMINARY
XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
DECEMBER 2000
REV. P1.0.5
GENERAL DESCRIPTION
The XRT82L34 is a fully integrated Quad (four chan-
nels) short-haul line interface unit for T1(1.544Mbps)
100
and E1(2.048Mbps) 75
or 120
applications.
Each channel consists of a receiver with equalizer for
reliable data and clock recovery, and a transmitter
which accepts either single or dual-rail digital inputs
for signal transmission to the line using a low output
impedance line driver. The device also includes a
crystal-less jitter attenuator which, depending on sys-
tem requirements, can be selected in the receive or
transmit path through the Host or Hardware Mode
control.
XRT82L34 is a low power CMOS device operating on
a single 3.3V supply with 5V tolerant digital inputs.
FEATURES
Fully integrated quad, short-haul PCM transceivers
for E1 and T1 applications.
On Chip Receive Equalizer and Transmit Pulse
Shaper for DS1 Digital Cross Connect (DSX-1) and
CEPT 75
and 120
line terminations
On chip clock recovery circuit
Transformer or capacitor coupled receiver inputs
Crystal-less jitter attenuator can be selected in the
transmit or receive path
High receiver interference immunity
Per-channel transmit power shutdown
Tri-state transmit output capability
On chip per-channel driver failure monitoring circuit
On chip HDB3/B8ZS/AMI encoder/decoder func-
tions
Transmit return loss meets or exceeds ETSI 300
166 standard
Meets or exceeds specifications in ITU G.703,
G.775, G.736 and G.823; Bellcore GR-499-CORE;
ANSI T1.403 and ETSI 300-166
3.3V or 5.0V Logic level inputs
Single +3.3V Supply Operation
APPLICATIONS
Digital cross connects (DSX-1)
Channel Banks
High speed data transmission line cards
T1/E1 Multiplexer
Public switching systems and PBX interfaces
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT82L34 T1/E1/J1 LIU (H
OST
M
ODE
)
HDB3/
B8ZS
Encoder
MUX
Tx/Rx Jitter
Attenuator
Tx Timing
Control
Tx Pulse
Shaper
MUX
Line
Driver
Tx/Rx Jitter
Attenuator
Timing & Data
Recovery
Peak
Detector
& Slicer
Rx
Equalizer
LOS
Detect
HDB3/
B8ZS
Decoder
Clock
Generator
MClk
TVDD[n]
TTIP[n]
TRing[n]
TGND[n]
Enable/
Disable
RTIP[n]
RRing[n]
Remote
LoopBack
Local
Analog
LoopBack
Digital
LoopBack
Driver
Monitor
Channel 0
Channel 1
Channel 2
Channel 3
HW/HOST
μ
P Controller & Hardware Interface
ADD [0:3]
D[0:7]
WR_R/W/TxOFF0
ALE_AS/TxOFF2
CS/TxOFF3
RD_DS/TxOFF1
Test
TxClk[n]
TxPOS[n]/TDATA[n]
TxNEG[n]
RxClk[n]
RxPOS[n]/RDATA[n]
RxNEG[n]/LCV[n]
RxLOS[n]
INT
RDY_DTACK
PClk/Codes
PTS1/ClkE
PTS2/SR_DR
Reset
ICT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT82L38 | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）) |
| XRT83D10 | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10IW | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83L314 | 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT |
| XRT83L314IB | 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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