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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� XRT83L34IV-F
寤犲晢锛� Exar Corporation
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 47/99闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC LIU T1/E1/J1 QUAD 128TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 72
椤炲瀷锛� 绶氳矾鎺ュ彛瑁濈疆锛圠IU锛�
椹�(q奴)鍕�(d貌ng)鍣�/鎺ユ敹鍣ㄦ暩(sh霉)锛� 4/4
瑕�(gu墨)绋嬶細 T1锛孍1锛孞1
闆绘簮闆诲锛� 3.135 V ~ 3.465 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 128-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 128-TQFP锛�14x20锛�
鍖呰锛� 鎵樼洡(p谩n)
鍏跺畠鍚嶇ū锛� XRT83L34IV-F-ND
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xr
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1
48
DIGITAL LOOP-BACK (DLOOP)
Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in Figure 23.
DUAL LOOP-BACK
Figure 24 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path
will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.
FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH
FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
Tx
Decoder
Timing
Control
Rx
Data &
Clock
Recovery
JA
TPOS
TNEG
TCLK
RCLK
RPOS
RNEG
Encoder
TTIP
TRING
RTIP
RRING
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鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

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*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣(g貌u)

鎴戠殑鑱�(li谩n)绯绘柟寮�

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