TABLE
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� XRT83L34IV-F
寤犲晢锛� Exar Corporation
鏂囦欢闋佹暩(sh霉)锛� 76/99闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC LIU T1/E1/J1 QUAD 128TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 72
椤炲瀷锛� 绶氳矾鎺ュ彛瑁濈疆锛圠IU锛�
椹�(q奴)鍕�(d貌ng)鍣�/鎺ユ敹鍣ㄦ暩(sh霉)锛� 4/4
瑕�(gu墨)绋嬶細 T1锛孍1锛孞1
闆绘簮闆诲锛� 3.135 V ~ 3.465 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 128-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 128-TQFP锛�14x20锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� XRT83L34IV-F-ND
XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
75
TABLE 28: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION
REGISTER ADDRESS
0001000
0011000
0101000
0111000
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
R/W
0
D6-D0
B6S1_n -
B0S1_n
Arbitrary Transmit Pulse Shape, Segment 1:The shape of
each channel's transmitted pulse can be made independently
user programmable by selecting 鈥淎rbitrary Pulse鈥� mode in
Table 5. The arbitrary pulse is divided into eight time seg-
ments whose combined duration is equal to one period of
MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the first time segment. B6S1_n-
B0S1_n is in signed magnitude format with B6S1_n as the
sign bit and B0S1_n as the least significant bit (LSB).
R/W
0
TABLE 29: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION
REGISTER ADDRESS
0001001
0011001
0101001
0111001
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
R/W
0
D6-D0
B6S2_n -
B0S2_n
Arbitrary Transmit Pulse Shape, Segment 2
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting 鈥淎rbitrary
Pulse鈥� mode in
Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the second time segment. B6S2_n-
B0S2_n is in signed magnitude format with B6S2_n as the
sign bit and B0S2_n as the least significant bit (LSB).
R/W
0
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
XRT83L38IB-F IC LIU T1/E1/J1 OCTAL 225BGA
XRT83SH314IB-F IC LIU T1/E1/J1 14CH 304TBGA
XRT83SH38IB-F IC LIU SH T1/E1/J1 8CH 225BGA
XRT86L30IV-F IC LIU/FRAMER TI/E1/J1 SGL 128LQ
XRT86VL30IV-F IC FRAMR/LIU T1/E1/J1 QD 128LQFP
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
XRT83L34IVTR 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕�(d貌ng)鍣ㄨ垏鍘熶欢 - PCI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray
XRT83L34IVTR-F 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕�(d貌ng)鍣ㄨ垏鍘熶欢 - PCI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray
XRT83L38 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83L38_07 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83L38ES 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕�(d貌ng)鍣ㄨ垏鍘熶欢 - PCI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�锛屽～瀵竴琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

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*鍨嬭櫉 *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

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