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參數(shù)資料
| 型號： | XRT83SL216IB-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 29/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SH E1 16CH 289STBGA |
| 標準包裝： | 84 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 16/16 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-LFBGA |
| 供應商設備封裝： | 289-STBGA（15x15） |
| 包裝： | 托盤 |
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XRT83SL216
33
REV. 1.0.0
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
D5
ATAOS_n
Automatic Transmit All Ones
If ATAOS_n is selected, an all ones pattern will be transmitted from
TTIP/TRING if the channel experiences an RLOS condition. If
RLOS does not occur, ATAOS_n will remain inactive.
"0" = Disabled
"1" = Enabled
R/W
0
D4
TAOS_n
Transmit All Ones
If TAOS_n is selected, an all ones pattern will be transmitted from
TTIP/TRING if the transmitter is turned on. Remote Loop Back
has priority over TAOS.
"0" = Disabled
"1" = Enabled
R/W
0
D3
RLAM_n
RLOS/AIS Mode Select for channel n
This bit is used to select the industry standard for declaring / clear-
ing RLOS and AIS functionality. See the Receive section of the
Line Interface description.
"0" = ITU G.775
"1" =ETSI300233
R/W
0
D2
TXOE_n
Transmit Output Enable
Upon power up, the tranmitters are tri-stated. This bit is used to
enable the transmitter for this channel if the TxOE pin is pulled
"High". If the TxOE pin is pulled "Low", all 8 transmitters are tri-
stated.
"0" = Transmitter is disabled
"1" = Transmitter is enabled if TxOE pin is pulled "High"
R/W
0
D1
RCLKinv_n
Receiver Clock Invert
This bit is used to invert receive clock update edge with respect to
RPOS/RNEG output data.
"0" =RPOS/RNEG data is updated on the rising edge of RCLK
"1" =RPOS/RNEG data is updated on the falling edge of RCLK.
R/W
0
D0
TCLKinv_n
Transmit Clock Invert
This bit is used to invert transmit clock sampling edge with respect
to TPOS/TNEG input data.
"0" =TPOS/TNEG data is sampled on the falling edge of TCLK
"1" =TPOS/TNEG data is sampled on the rising edge of TCLK.
R/W
0
TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION
CHANNEL CONTROL REGISTER (CHANNEL_n, where n = 0:15)
(0X06H, 0X09H, 0X0CH, 0X0FH, 0X12H, 0X15H, 0X18H, 0X1BH, 1EH, 0X21H, 0X24H, 0X27H, 0X2AH, 0X2DH, 0X30H, 0X33H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
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