XRT83VSH314
64
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 44: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION
GLOBAL REGISTER (0XE4H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
MCLKT1out1
MCLKT1out0
MCLKT1Nout Select
MclkT1out[1:0] is used to program the MCLKT1out pin. By default,
the output clock is 1.544MHz.
00 = 1.544MHz
01 = 3.088MHz
10 = 6.176MHz
11 = 12.352MHz
R/W
0
D5
D4
MCLKE1out1
MCLKE1out0
MCLKE1Nout Select
MclkE1out[1:0] is used to program the MCLKE1Nout pin.
By
default, the output clock is 2.048MHz.
00 = 2.048MHz
01 = 4.096MHz
10 = 8.192MHz
11 = 16.384MHz
R/W
0
D[3:0]
Reserved
These Register Bits are Not Used
R/W
0
TABLE 45: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION
GLOBAL REGISTER (0XE5H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
LCV_OFLW Line Code Violation / Counter Overflow Monitor Select
This bit is used to select the monitoring activity between the LCV
and the counter overflow status. When the 16-bit LCV counter sat-
urates, the counter overflow condition is activated. By default, the
LCV activity is monitored by bit D4 in register 0x05h.
0 = Monitoring LCV
1 = Monitoring the counter overflow status
R/W
0
D6
Reserved
R/W
0
D5
Reserved
This Register Bit is Not Used
R/W
0