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XRT86L30
227
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
2. Each interval with a valid YEL flag increments a flag counter which declares YEL alarm when 80 valid
intervals have been accumulated.
3. An interval without valid YEL flag decrements the flag counter. The YEL alarm is removed when the
counter reaches zero.
If Yellow Alarm condition is present in the incoming DS1 frame, the XRT86L30 framer can generate a Receive
Yellow Alarm State Change interrupt associated with the setting of Receive Yellow Alarm State Change bit of
the Alarm and Error Status Register to one.
To enable the Receive Yellow Alarm State Change interrupt, the Receive Yellow Alarm State Change Interrupt
Enable bit of the Alarm and Error Interrupt Enable Register (AEIER) has to be set to one. In addition, the Alarm
and Error Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive Yellow Alarm State Change Interrupt Enable bit of the
Alarm and Error Interrupt Enable Register (AEIER).
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
When these interrupt enable bits are set and Yellow Alarm is present in the incoming DS1 frame, the
XRT86L30 framer will declare Yellow Alarm by doing the following:
Set the read-only Receive Yellow Alarm State bit of the Alarm and Error Status Register (AESR) to one
indicating there is Yellow Alarm detected in the incoming DS1 frame.
Set the Receive Yellow Alarm State Change bit of the Alarm and Error Status Register to one indicating there
is a change in state of Yellow Alarm. This status indicator is valid until the Framer Interrupt Status Register is
read.
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (ADDRESS = 0X0B03H)
BIT
NUMBER
BIT NAME
BIT TYPE
BIT DESCRIPTION
0
Receive Yellow
Alarm State
Change Interrupt
Enable
R/W
0 - The Receive Yellow Alarm State Change interrupt is disabled. Any state
change of Receive Yellow Alarm will not generate an interrupt.
1 - The Receive Yellow Alarm State Change interrupt is enabled. Any state
change of Receive Yellow Alarm will generate an interrupt.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (ADDRESS = 0X0B01H)
BIT
NUMBER
BIT NAME
BIT TYPE
BIT DESCRIPTION
1
Alarm and Error
Interrupt Enable
R/W
0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.