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參數(shù)資料
型號: XRT86VL32IB
廠商: Exar Corporation
文件頁數(shù): 11/155頁
文件大?。?/td> 0K
描述: IC LIU/FRAMER T1/E1/J1 2CH 225BG
標(biāo)準(zhǔn)包裝: 84
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT86VL32
103
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
4
SLC
96 LOCK
RO
0
SLC
96 is in SYNC
This READ ONLY bit field indicates whether or not frame synchroni-
zation is achieved when the XRT86VL32 is configured in SLC
96
framing mode.
0 = Indicates that frame synchronization is not achieved in SLC
96
framing mode.
1 = Indicates that frame synchronization is achieved in SLC
96
framing mode.
3
Multiframe LOCK
RO
0
Multiframe is in SYNC
This READ ONLY bit field indicates whether or not the T1 Receive
Framer Block is declaring T1 Multiframe LOCK status.
0 = Indicates that the T1 Receive Framer is currently declaring T1
multiframe LOSS OF LOCK status
0 = Indicates that the T1 Receive Framer is currently declaring T1
multiframe LOCK status
2
RxSB_FULL
RUR/
WC
0
Receive Slip buffer Full Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receive Slip
Buffer Full interrupt has occurred since the last read of this register.
The Receive Slip Buffer Full interrupt is declared when the receive
slip buffer is filled. If the receive slip buffer is full and a WRITE oper-
ation occurs, then a full frame of data will be deleted, and this inter-
rupt bit will be set to ‘1’.
0 = Indicates that the Receive Slip Buffer Full interrupt has not
occurred since the last read of this register.
1 = Indicates that the Receive Slip Buffer Full interrupt has occurred
since the last read of this register.
TABLE 86: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR)
HEX ADDRESS: 0XnB08
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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