參數(shù)資料
型號： XRT86VL34IB-F
廠商： Exar Corporation
文件頁數(shù)： 3/155頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 4CH 225BG
標準包裝： 84
控制器類型： T1/E1/J1 調幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應商設備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL34
95
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.1
2
FMD
RUR/
WC
0
Frame Mimic Detection Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “Frame Mimic
Detection” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will
generate an interrupt whenever the Receive T1 Framer block detects the
presence of Frame Mimic bits (i.e., the Payload bits have appeared to
mimic the Framing Bit pattern within the incoming T1 data stream).
0 = Indicates that the “Frame Mimic Detection” interrupt has not occurred
since the last read of this register.
1 = Indicates that the “Frame Mimic Detection” interrupt has occurred
since the last read of this register.
1
SE
RUR/
WC
0
Synchronization Bit Error (CRC-6) Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “CRC-6 Error”
interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will
generate an interrupt whenever the Receive T1 Framer block detects a
CRC-6 Error within the incoming T1 multiframe.
0 = Indicates that the “CRC-6 Error” interrupt has not occurred since the
last read of this register.
1 = Indicates that the “CRC-6 Error” interrupt has occurred since the last
read of this register.
0
FE
RUR/
WC
0
Framing Error Interrupt Status
This Reset-Upon-Read bit field indicates whether or not a “Framing Error”
interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will
generate an interrupt whenever the Receive T1 Framer block detects one
or more Framing Alignment Bit Error within the incoming T1 data stream.
0 = Indicates that the “Framing Error” interrupt has not occurred since the
last read of this register.
1 = Indicates that the “Framing Error” interrupt has occurred since the last
read of this register.
NOTE: This bit doesn't not necessarily indicate that synchronization has
been lost.
TABLE 82: FRAMER INTERRUPT STATUS REGISTER (FISR)
HEX ADDRESS: 0XnB04
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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