TABLE
參數(shù)資料
型號(hào)： XRT86VL34IB-F
廠商： Exar Corporation
文件頁數(shù)： 50/155頁
文件大小： 0K
描述： IC LIU/FRAMER T1/E1/J1 4CH 225BG
標(biāo)準(zhǔn)包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL34
138
REV. V1.2.1
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 113: LIU CHANNEL CONTROL INTERRUPT STATUS REGISTER (LIUCCISR)
HEX ADDRESS: 0X0FN6
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
RO
0
6
DMOIS_n
RUR/
WC
0
Change of Transmit DMO (Drive Monitor Output) Condition
Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Change of
the Transmit DMO Condition” Interrupt has occurred since the last
read of this register.
0 = Indicates that the “Change of the Transmit DMO Condition”
Interrupt has NOT occurred since the last read of this register.
1 = Indicates that the “Change of the Transmit DMO Condition”
Interrupt has occurred since the last read of this register.
This bit is set to a “1” every time when DMO_n status bit (bit 6 of
Register 0x0Fn5) has changed since the last read of this register.
NOTE: Users can determine the current state of the “Transmit DMO
Condition” by reading out the content of bit 6 within Register
0x0Fn5
5
FLSIS_n
RUR/
WC
0
FIFO Limit Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “FIFO
Limit” Interrupt has occurred since the last read of this register.
0 = Indicates that the “FIFO Limit Status” Interrupt has NOT
occurred since the last read of this register.
1 = Indicates that the “FIFO Limit Status” Interrupt has occurred
since the last read of this register.
This bit is set to a “1” every time when FIFO Limit Status bit (bit 5 of
Register 0x0Fn5) has changed since the last read of this register.
NOTE: Users can determine the current state of the “FIFO Limit” by
reading out the content of bit 5 within Register 0x0Fn5
4
LCVIS_n
RUR/
WC
-
Line Code Violation Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Line Code
Violation” Interrupt has occurred since the last read of this register.
0 = Indicates that the “Line Code Violation” Interrupt has NOT
occurred since the last read of this register.
1 = Indicates that the “Line Code Violation” Interrupt has occurred
since the last read of this register.
This bit is set to a “1” every time when Line Code Violation Status bit
(bit 4 of Register 0x0Fn5) has changed since the last read of this
register.
Users can determine the current state of the “Line Code Violation”
by reading out the content of bit 4 within Register 0x0Fn5
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