XRT86VL38
109
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.1
3
LCV Int Status
RUR/
WC
0
Line Code Violation Interrupt Status
.
This Reset-Upon-Read bit field indicates whether or not the Receive E1 LIU
block has detected a Line Code Violation interrupt since the last read of this
register.
0 = Indicates that the Line Code Violation interrupt has not occurred since
the last read of this register.
1 = Indicates that the Line Code Violation interrupt has occurred since the
last read of this register.
2
Rx LOF State
Change
RUR/
WC
0
Change in Loss of Frame Condition Interrupt Status
.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive Loss of Frame Condition” interrupt has occurred since the last read
of this register.
If this interrupt is enabled, then the Receive E1 Framer block will generate
an interrupt in response to either one of the following
conditions.
1.
Whenever the Receive E1 Framer block declares the Loss of Frame
condition.
2.
Whenever the Receive E1 Framer block clears the Loss of Frame
condition
0 = Indicates that the “Change in Receive Loss of Frame condition” interrupt
has not occurred since the last read of this register
1 = Indicates that the “Change in Receive Loss of Frame condition” interrupt
has occurred since the last read of this register
1
RxAIS State
Change
RUR/
WC
0
Change in Receive AIS Condition Interrupt Status
.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive AIS Condition” interrupt has occurred since the last read of this reg-
ister.
If this interrupt is enabled, then the Receive E1 Framer block will generate
an interrupt in response to either one of the following conditions.
1.
Whenever the Receive E1 Framer block declares the AIS condition.
2.
Whenever the Receive E1 Framer block clears the AIS condition
0 = Indicates that the “Change in Receive AIS condition” interrupt has not
occurred since the last read of this register
1 = Indicates that the “Change in Receive AIS condition” interrupt has
occurred since the last read of this register
0
RxYEL State
Change
RUR/
WC
0
Change in Receive Yellow Alarm Interrupt Status.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive Yellow Alarm Condition” interrupt has occurred since the last read
of this register.
If this interrupt is enabled, then the Receive E1 Framer block will generate
an interrupt in response to either one of the following conditions.
1.
Whenever the Receive E1 Framer block declares the Yellow Alarm
condition.
2.
Whenever the Receive E1 Framer block clears the Yellow Alarm
condition
0 = Indicates that the “Change in Receive Yellow Alarm condition” interrupt
has not occurred since the last read of this register
1 = Indicates that the “Change in Receive Yellow Alarm condition” interrupt
has occurred since the last read of this register
T
ABLE
97: A
LARM
& E
RROR
I
NTERRUPT
S
TATUS
R
EGISTER
(AEISR) H
EX
A
DDRESS
: 0
X
nB02
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION