
XRT86VL38
IV
REV. V1.2.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
Table 59:: Receive Data Link Byte Count Register (RDLBCR2) Hex Address: 0xn145 ................ 76
Table 60:: Data Link Control Register (DLCR3) Hex Address: 0xn153 ................ 77
Table 61:: Transmit Data Link Byte Count Register (TDLBCR3) Hex Address: 0xn154 ................. 79
Table 62:: Receive Data Link Byte Count Register (RDLBCR3) Hex Address: 0xn155 ............... 80
Table 63:: Device ID Register (DEVID) Hex Address: 0xn1FE ............. 81
Table 64:: Revision ID Register (REVID) Hex Address: 0xn1FF .......... 81
Table 65:: Transmit Channel Control Register 0-31 (TCCR 0-31) Hex Address: 0Xn300 to 0xn31F ................... 82
Table 66:: Transmit User Code Register 0 - 31 (TUCR 0-31) Hex Address: 0xn320 to 0xn33F .............. 84
Table 67:: Transmit Signaling Control Register 0-31 (TSCR 0-31) Hex Address: 0xn340 to 0xn35F ................... 85
Table 68:: Receive Channel Control Register x (RCCR 0-31) Hex Address: 0xn360 to 0xn37F ................. 88
Table 69:: Receive User Code Register 0-31 (RUCR 0-31) Hex Address: 0xn380 to 0xn39F ............... 90
Table 70:: Receive Signaling Control Register 0-31 (RSCR 0-31) Hex Address: 0xn3A0 to 0xn3BF ................... 91
Table 71:: Receive Substitution Signaling Register 0-31 (RSSR 0-31) Hex Address 0xn3C0 to 0xn3DF .................. 93
Table 72:: Receive Signaling Array Register 0 - 31 (RSAR 0-31) Hex Address: 0Xn500 to 0xn51F ................. 94
Table 73:: LAPD Buffer 0 Control Register (LAPDBCR0) Hex Address: 0xn600 .................................... 95
Table 74:: LAPD Buffer 1 Control Register (LAPDBCR1) Hex Address: 0xn700 .................................... 95
Table 75:: PMON Receive Line Code Violation Counter MSB (RLCVCU) Hex Address: 0xn900 ................. 96
Table 76:: PMON Receive Line Code Violation Counter LSB (RLCVCL) Hex Address: 0xn901 ................ 96
Table 77:: PMON Receive Framing Alignment Bit Error Counter MSB (RFAECU) Hex Address: 0xn902 ................... 97
Table 78:: PMON Receive Framing Alignment Bit Error Counter LSB (RFAECL) Hex Address: 0xn903 .................... 97
Table 79:: PMON Receive Severely Errored Frame Counter (RSEFC) Hex Address: 0xn904 .................... 98
Table 80:: PMON Receive CRC-4 Bit Error Counter - MSB (RSBBECU) Hex Address: 0xn905 ................... 98
Table 81:: PMON Receive CRC-4 Block Error Counter - LSB (RSBBECL) Hex Address: 0xn906 .................... 98
Table 82:: PMON Receive Far-End BLock Error Counter - MSB (RFEBECU) Hex Address: 0xn907 .................. 99
Table 83:: PMON Receive Far End Block Error Counter -LSB (RFEBECL) Hex Address: 0xn908 .................... 99
Table 84:: PMON Receive Slip Counter (RSC) Hex Address: 0xn909 ........... 100
Table 85:: PMON Receive Loss of Frame Counter (RLFC) Hex Address: 0xn90A ............. 100
Table 86:: PMON Receive Change of Frame Alignment Counter (RCFAC) Hex Address: 0xn90B ............... 100
Table 87:: PMON LAPD Frame Check Sequence Error Counter 1 (LFCSEC1) Hex Address: 0xn90C ............... 101
Table 88:: PMON PRBS Bit Error Counter MSB (PBECU) Hex Address: 0xn90D ............101
Table 89:: PMON PRBS Bit Error Counter LSB (PBECL) Hex Address: 0xn90E ........... 101
Table 90:: PMON Transmit Slip Counter (TSC) Hex Address: 0xn90F ........... 102
Table 91:: PMON Excessive Zero Violation Counter MSB (EZVCU) Hex Address: 0xn910 ................ 102
Table 92:: PMON Excessive Zero Violation Counter LSB (EZVCL) Hex Address: 0xn911 ................ 102
Table 93:: PMON Frame Check Sequence Error Counter 2 (LFCSEC2) Hex Address: 0xn91C ................ 103
Table 94:: PMON Frame Check Sequence Error Counter 3 (LFCSEC3) Hex Address: 0xn92C ................ 103
Table 95:: Block Interrupt Status Register (BISR) Hex Address: 0xnB00 ................... 104
Table 96:: Block Interrupt Enable Register (BIER) Hex Address: 0xnB01 .................. 106
Table 97:: Alarm & Error Interrupt Status Register (AEISR) Hex Address: 0xnB02 ...................... 108
Table 98:: Alarm & Error Interrupt Enable Register (AEIER) Hex Address: 0xnB03 ..................... 110
Table 99:: Framer Interrupt Status Register (FISR) Hex Address: 0xnB04 ................ 112
Table 100:: Framer Interrupt Enable Register (FIER) Hex Address: 0xnB05 .............. 115
Table 101:: Data Link Status Register 1 (DLSR1) Hex Address: 0xnB06 ............ 117
Table 102:: Data Link Interrupt Enable Register 1 (DLIER1) Hex Address: 0xnB07 ................. 119
Table 103:: Slip Buffer Interrupt Status Register (SBISR) Hex Address: 0xnB08 ................ 121
Table 104:: Slip Buffer Interrupt Enable Register (SBIER) Hex Address: 0xnB09 ................... 124
Table 105:: Receive Loopback Code Interrupt and Status Register (RLCISR) Hex Address: 0xnB0A ................... 126
Table 106:: Receive Loopback Code Interrupt Enable Register (RLCIER) Hex Address: 0xnB0B ................ 128
Table 107:: Receive SA Interrupt Status Register (RSAISR) Hex Address: 0xnB0C .............. 129
Table 108:: Receive SA Interrupt Enable Register (RSAIER) Hex Address: 0xnB0D .............. 132
Table 109:: Excessive Zero Status Register (EXZSR) Hex Address: 0xnB0E ........... 135
Table 110:: Excessive Zero Enable Register (EXZER) Hex Address: 0xnB0F ............ 136
Table 111:: SS7 Status Register for LAPD1 (SS7SR1) Hex Address: 0xnB10 .............. 136
Table 112:: SS7 Enable Register for LAPD1 (SS7ER1) Hex Address: 0xnB11 ............ 137
Table 113:: RxLOS/CRC Interrupt Status Register (RLCISR) Hex Address: 0xnB12 ............. 137
Table 114:: RxLOS/CRC Interrupt Enable Register (RLCIER) Hex Address: 0xnB13 .............139
Table 115:: Data Link Status Register 2 (DLSR2) Hex Address: 0xnB16 .............. 140
Table 116:: Data Link Interrupt Enable Register 2 (DLIER2) Hex Address: 0xnB17 ................ 142
Table 117:: SS7 Status Register for LAPD2 (SS7SR2) Hex Address: 0xnB18 .............. 144
Table 118:: SS7 Enable Register for LAPD2 (SS7ER2) Hex Address: 0xnB19 .............. 144