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參數資料
| 型號： | XRT91L30_0611 |
| 廠商： | Exar Corporation |
| 英文描述： | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| 中文描述： | STS-12/STM-4或STS-3/STM-1的SONET / SDH收發(fā)器 |
| 文件頁數： | 27/39頁 |
| 文件大小： | 440K |
| 代理商： | XRT91L30_0611 |
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xr
REV. 1.0.1
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
25
3.6
The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS-
12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential
LVPECL input REFCLKP/N accepts a clock reference of 77.76 MHz or 19.44 MHz to synthesize a high speed
622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a
Differential LVPECL clock source is not available, TTLREFCLK can accept an LVTTL clock signal. The clock
synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK
reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary
accuracy required for SONET systems. If the TTLREFCLK reference clock is used, the TTLREFCLK
reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are
XNOR’ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or
TTLREFCLK to ground. Table 1, on page 12 shows the CMU reference clock frequency settings. Table 14
specifies the Clock Multiplier Unit’s requirements for the Reference clock.
T
ABLE
14: C
LOCK
M
ULTIPLIER
U
NIT
’
S
R
EQUIREMENTS
FOR
R
EFCLK
Clock Multiplier Unit (CMU) and Re-Timer
Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.
1
These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUI
rms
).
2
Required to meet SONET output frequency stability requirements.
3.7
Two types of loop timing are possible in the XRT91L30.
In the internal loop timing mode, loop timing is controlled by the LOOPTIME pin. This mode is selected by
asserting the LOOPTIME signal to a high level. When the loop timing mode is activated, the CMU synthesized
hi-speed reference clock input to the Retimer is replaced with the hi-speed internally recovered receive clock
coming from the CDR. Under this condition both the transmit and receive sections are synchronized to the
internally recovered receive clock. Loop time mode directly locks the Retimer to the recovered receive clock.
In external loop timing mode, the XRT91L30 allows the user the flexibility of using an externally recovered
receive clock for retiming the high speed serial data. First, the CDRDIS input pin should be set high. By doing
so, the internal CDR is disabled and bypassed and the XRT91L30 will sample the incoming high speed serial
data on RXIP/N with the externally recovered receive clock connected to the XRXCLKIP/N inputs. In this state,
the receive clock de-jittering and recovery is done externally and fed thru XRXCLKIP/N and the XRT91L30 will
sample RXIP/N on the rising edge of XRXCLKIP/N. Secondly, the LOOPTIME pin must also be set high in
order to select the externally recovered receive clock on XRXCLKIP/N as the reference clock source for the
transmit serial data output stream TXOP/N.
Loop Timing and Clock Control
N
AME
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
REF
DUTY
Reference clock duty cycle
40
60
%
REF
JIT
Reference clock jitter (rms) with 19.44 MHz reference
1
5
ps
REF
JIT
Reference clock jitter (rms) with 77.76 MHz reference
1
13
ps
REF
TOL
Reference clock frequency tolerance
2
-20
+20
ppm
相關PDF資料 |
PDF描述 |
|---|---|
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT91L306 | 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30ES | 功能描述:總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L30IQ | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT91L30IQ-F | 功能描述:網絡控制器與處理器 IC 8-Bit TTL 3.3V temp -45 to 85C;UART RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT91L30IQ-F | 制造商:Exar Corporation 功能描述:SONET Transceiver IC |
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