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參數(shù)資料
| 型號： | XRT91L306 |
| 廠商： | Exar Corporation |
| 英文描述： | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| 中文描述： | STS-12/STM-4或STS-3/STM-1的SONET / SDH收發(fā)器 |
| 文件頁數(shù)： | 25/39頁 |
| 文件大?。?/td> | 440K |
| 代理商： | XRT91L306 |
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xr
REV. 1.0.1
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
23
3.3
To decouple transmit parallel clock domains of the framer/mapper device and the XRT91L30 transceiver and to
eliminate difficult timing issues between them, the transmit parallel clock TXPCLK_IO can also be optionally
configured as a clock input. Rather than provide a transmit parallel clock output reference to the framer/mapper
device, the XRT91L30 can instead accept a reference transmit parallel clock input signal from the framer/
mapper device to sample the transmit parallel bus. When PIO_CTRL pin 48 is asserted "Low," TXPCLK_IO
switches into a clock input and the XRT91L30 will now sample data on the transmit parallel bus TXDI[7:0]
based on TXPCLK_IO clock input reference coming from the framer/mapper device. The use of the alternate
transmit parallel bus clock input option permits the system to tolerate an arbitrary amount of phase mismatch
and jitter between framer/mapper transmit parallel clock timing and transceiver transmit timing. Figure 13
provides a detailed overview of the alternate transmit parallel bus clock input system interface.
Alternate Transmit Parallel Bus Clock Input Option
3.4
When applying parallel data input to the transmitter in the alternate transmit parallel bus clock input mode of
operation, the setup and hold times should be followed as shown in Figure 14 and Table 12, Table 13.
F
IGURE
14. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
Alternate Transmit Parallel Data Input Timing
F
IGURE
13. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
(P
ARALLEL
C
LOCK
I
NPUT
O
PTION
)
SONET Framer/ASIC
TXPCLK_IO
XRT91L30
STS-12/STM-4
or
STS-3/STM-1
Transceiver
TXDI[7:0]
8
(Parallel Clock Input Option)
REFCLKP
TTLREFCLK
CMUFREQSEL
REFCLKN
PIO_CTRL
t
TXPCLK_IO
TXDI[7:0]
TXPCLK_IO
t
TXDI_HD
t
TXDI_SU
Alternate Transmit Parallel Clock Input Option
Transmit Parallel
Clock driven by
Framer/Mapper
Device
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L32 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L30ES | 功能描述:總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L30IQ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT91L30IQ-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Bit TTL 3.3V temp -45 to 85C;UART RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT91L30IQ-F | 制造商:Exar Corporation 功能描述:SONET Transceiver IC |
| XRT91L30IQTR | 功能描述:總線收發(fā)器 RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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